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^Eagle^ 12/5/2012 | 4:12:59 PM
re: Nortel Shows Single-Slice 100GE Ian,

Thanks for the link. However, this announcement by Fuji is not an asic for the processing that needs to be done. This is just an ADC chip. 1 small part of the electronics that need to be developed. An important part, but the ADC is not the ASIC.

My previous comment and question stands.

IJD 12/5/2012 | 4:12:59 PM
re: Nortel Shows Single-Slice 100GE In answer to the "does anyone have a 100G coherent receiver ASIC in the works" I guess you can draw your own conclusions from the information here


and the recent press releases.

IJD 12/5/2012 | 4:12:58 PM
re: Nortel Shows Single-Slice 100GE Absolutely correct -- but my post was really in reply to the question "is anyone developing a real production-worthy 100G DP-DQPSK coherent receiver ADC/DSP ASIC?"

The answer is yes, somebody obviously is ;-)

Doing the DSP digital for such an ASIC is not easy but can be done; integrating it with multiple 56Gs/s CMOS ADCs is crucial to get the power and cost down, and this IP just didn't exist before.

As you say, the ADC is not the ASIC -- but the ADC technology is our IP so we can talk about it (and offer it to other users), the ASIC is our partner's so we can't...

Ian (Fujitsu Microelectronics)
^Eagle^ 12/5/2012 | 4:12:57 PM
re: Nortel Shows Single-Slice 100GE Ian,

Thanks for the clarification and additional detail. Understood and appreciated.

lightreadingusername 12/5/2012 | 4:12:53 PM
re: Nortel Shows Single-Slice 100GE

This is an impressive piece of work--56GSs, 8b, 2W,
in 65nm-CMOS.

Is there an explanation of what this CHAIS technology is? i.e. is this some non-standard CMOS based technology?

Second, the press release mentions two channels that are time-interleaved as I/Q. i.e. each channel has a VCO=17GHz, which is not a true 56GSs ADC. Assuming you are using a 1:2 sample/hold structure (sampling at 28GSs), and sampling two separate channels. The block diagram shows this, assuming two separate channels as I and Q coming in.

With a -3dB bandwidth of 15GHz, that's still a long way to go before getting to 28GHz.

Very cool ADC!

AutoDog 12/5/2012 | 4:12:51 PM
re: Nortel Shows Single-Slice 100GE If I were a betting man, I'd put my money on AlcaLu as the unnamed partner that is working with FME to build this alleged coherent receiver ASIC.

Further, I'd say it's most likely the folks in the Nurenberg, Germany office that have a long-standing relationship with FME. Recall they effectively contracted FME to build their 40G ASICs and later CoreOptics tried (but failed) to resell. My guess is that AlcaLu/FME have teamed up to do it again at 100G, minus the CoreOptics reselling arrangement which bombed.

I don't see any other big system players willing to pony-up the cash needed to do this. Nortel has their own in-house coherent receiver ASIC team but time will tell if they will commit to a respin it up to the rates necessary to do a true, single-lambda 100G PM-QPSK.

IJD 12/5/2012 | 4:12:47 PM
re: Nortel Shows Single-Slice 100GE A lot of betting people who thought they were onto a sure thing have lost their trousers recently...

From what's been made public it's no secret that there are probably quite a few network companies (like Alcatel-Lucent) and solution providers (like CoreOptics) -- but probably few or no semiconductor suppliers (like FME) -- who have the knowledge to design a true single-lambda 100G PM-QPSK receiver, always provided they can access the ADC technology required which has been the big stumbling block:


There's a shorter list (but still mysteriously longer then 1... :-) with the resources (including subcontract design) to turn this into an ASIC together with FME, the precise meaning of ASIC here being either customer-specific or open-market depending on the business model.

AFAIK Nortel have the only single-chip 40G coherent receiver, but taking the ADCs from 20Gs/s up to 56Gs/s is a very tall order for conventional ADC technology, as the above reference points out...

IJD 12/5/2012 | 4:12:47 PM
re: Nortel Shows Single-Slice 100GE Thanks for the compliment !

As the release says it's a standard 65nm CMOS process, and no there isn't any public information about how CHAIS works -- when we're confident that the IP is protected we can reveal more, but you know how long and drawn-out the patent process is...

If you go to www.chais.info you can download a flyer for the ADC which shows more detail about it. Each ADC (I or Q, H or V) samples the input simultaneously at 56Gs/s even though the VCO is at 14GHz, I expect you can work out how this is possible ;-)

The 3dB frequency at 15GHz includes package loss as well as ADC frequency response; this bandwidth is predictable and can be digitally compensated for to push the 3dB point up to 25MHz or so if desired, the noise penalty to do this is only a couple of dB.


teleliar 12/5/2012 | 4:12:41 PM
re: Nortel Shows Single-Slice 100GE Ian,

CHAIS looks like a similar technology from:

at higher rates.
IJD 12/5/2012 | 4:12:41 PM
re: Nortel Shows Single-Slice 100GE Just because the description sounds similar doesn't mean that CHAIS and FemtoCharge *are* similar... ;-)

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