HILLSBORO, Ore. -- Lattice Semiconductor Corporation (Nasdaq:LSCC), the leader in programmable SERDES technology, today announced the availability of the ORSPI4, a Field Programmable System-on-a-Chip (FPSC) that efficiently integrates ASIC and FPGA technologies. By combining the two approaches, Lattice has developed a more highly integrated, higher performance, lower cost and lower power SPI4.2 solution when compared to a full FPGA implementation. The pre-engineered ASIC block on the ORSPI4 contains two SPI4.2 interface blocks, a high-speed Quad Data Rate (QDR II) SRAM memory controller, 4 channels of 600 Mbps to 3.7 Gigabits per second (Gbps) SERDES, 8b/10b encoding/decoding and other supporting logic. Connected to the ASIC block is a high performance FPGA with over 16,000 FPGA logic elements plus embedded block RAM. The ORSPI4 FPSC is the world's most highly integrated field programmable System-on-a-Chip targeted at line card applications for high-speed communications systems in the Metro space. "The ORSPI4 FPSC is the tenth FPSC product that Lattice has introduced into the market, but the first targeted specifically at a growing line card segment," said Stan Kopec, vice president of corporate marketing at Lattice. "Analysts expect line card shipments to rise from 1.9 million ports in 2002 to 4.8 million ports in 2006, a 27% compound annual growth rate (CAGR)(1), and Lattice will be there with a highly-integrated device that will bridge network processors, MACs and framers to high-speed serial backplanes," added Kopec. SPI4.2 (System-Packet Interface, Level 4, Phase 2) is a recent system-level interface standard that enables the development of flexible, scalable systems for a converged data and telecommunications infrastructure. Published in 2001 by the Optical Internetworking Forum (OIF), the SPI4.2 standard supports the transmission of multiple protocols at variable, high-speed data rates, including: Packet-over-SONET/SDH (POS), OC-192, Ethernet, Fast Ethernet, Gigabit Ethernet, 10 Gigabit Ethernet, and 10 Gigabit Fibre-Channel SAN. SPI4.2 eliminates proprietary ASIC-based or specialized network processor interfaces traditionally used to support a broad range of data rates and services. The benefits are a common standards-based interface facilitating inter-connection between diverse devices from multiple manufacturers. Designed for packet transfer between a MAC device and a network processor or switch fabric, the SPI4.2 interface supports the aggregate bandwidths required of ATM and Packet-over-SONET/SDH (POS) applications. SPI4.2 provides a common interface for 10 Gbps Wide Area Network (WAN), Local Area Network (LAN), Metro Area Network (MAN), and Storage Area Network (SAN) technologies, and it is ideal for systems that aggregate low-data rate channels into a single 10 Gbps uplink for long haul or backbone transmission. Lattice's ORSPI4 FPSC is unique in the programmable market as it embeds the SPI4.2 core in pre-characterized ASIC gates, unlike competitors who ship soft SPI4.2 IP cores which must be integrated into the overall design and face the uncertainties of FPGA place and route timing. Advantages Over FPGA-Only Approaches

"Unlike other SPI4.2 implementations for FPGAs, the ORSPI4 FPSC embeds all the high-speed functions in an ASIC core of over 1 million gates, allowing the FPGA gates to be used for design-specific bridging functions," commented Stan Kopec, vice president of marketing at Lattice. "Embedding these functions within a hard core assures performance, predictability and interoperability. This implementation also provides a big advantage in terms of total power consumption. Typical programmable-only FPGA IP cores consume upwards of 10W for one SPI4.2 interface implementation. In comparison, the ORSPI4 dissipates less than 2W per SPI4.2 implementation at 900 Mbps operation. This is a big advantage for power hungry 10 Gbps line cards," added Kopec. "Line cards are getting 'smarter' all the time, with the incorporation of NPUs and traffic management capabilities. This intelligence adds to board complexity with the potential for signal skew and strenuous layout constraints," added Kopec. "The SPI4.2 spec defines a de-skew technique that relies on a built-in training sequence with user-selectable repetition rate and duration. Referred to as dynamic alignment, this timing mode eliminates phase errors due to PCB traces of unequal lengths by continuously monitoring the data and adjusting the phase of the clock to align with it. This can be a challenging problem for programmable devices, but our FPSC technology affords us the opportunity to manage dynamic alignment with predictable and reliable ASIC technology," he concluded. Lattice Semiconductor Corp.