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Comms chips

EZchip Sallies Fourth

EZchip Technologies today became the fourth vendor to announce shipment of a full-fledged 10-Gbit/s network processor, a chip that sits inside switches, routers, and other packet-processing equipment (see EZchip Intros 10-Gig Processor).

First past the post in this particular race was startup Terago Communications Inc. (see Terago Springs a Surprise). It was followed by Applied Micro Circuits Corp. (AMCC) (Nasdaq: AMCC), the only established chipmaker to ship a 10-Gbit/s packet processor, and startup Bay Microsystems Inc. rounded out the top three (see AMCC Ships 10-Gbit/s Processor and Bay Joins the Big Leagues).

Despite being slightly behind these vendors in terms of its product schedule, EZchip's CEO Eli Fruchter says his company’s product is ahead of them in many respects. For starters, one of EZchip's customers has already designed the NP-1, as it's called, into a system, and said system will be demonstrated at EZchip's stand at the upcoming Networld+Interop show in Las Vegas in a couple weeks' time.

The name of the customer will be revealed in due course, says Fruchter. He says it is not a tier one, but adds that "the point is not the size of the customer, but the fact it is able to show a working system just one month after receiving [our] product."

One of main criticisms leveled at network processor vendors is that their products are too difficult to program. A short development time indicates that this particular customer didn't find the programming of EZchip's chip too onerous.

EZchip also claims it's got something special in terms of integration that will enable it to fast-forward past the competition. "There are lots of hidden costs [in packet processing cards] that can turn out to cost a customer a lot of money," says Fruchter.

Usually, a network processing chip has to be surrounded with banks of supporting chips -- mainly classification coprocessors and the associated memory chips -- and these chips make up a significant part of the cost, size, and power of the overall solution. Yet, Fruchter notes, these chips are rarely included when vendors make product comparisons.

If the supporting chips are taken into account, then EZchip has a solution with approximately one-fifth the chip count of competing solutions, he contends. This saving is due to the fact that the NP-1 includes embedded classifiers (search engines). "By embedding the classifier, we're saving 20 to 25 chips, 80 watts of power, and $3,500 in direct costs," Fruchter claims.

That's pretty significant, if true. Fruchter fleshes out the comparison with a chart, which is reproduced in table 1.

Table 1: Competitive Comparison
Complete Solution AMCC EZchip
Network processor 2 x $700, 30 W total power consumption 1x $1,150, 15 W power consumption
External memory/ search engines 12 CAMs, 12 SRAMs, $3,600, and 84 W in total 4 x DRAM, $25, and 2 W in total
Total number chips 26 chips 5 chips
Power consumption 114 W 17 W
Total cost $5,000 $1,175
Source: EZchip


AMCC is singled out for comparison, mostly because it's an incumbent and partly because, like EZchip, its product is a seven-layer processor -- in other words, it can perform lookups on data in the packet payload as well as in the packet header. The network processors from Bay and Terago can only process up to layer four (header lookups only).

The key differences are that AMCC's solution is half-duplex, so two chips are required; also, it requires a number of external CAMs (content addressable memory) and SRAMs (memory chips). EZchip's NP-1 is a full-duplex solution. Both vendors' solutions require separate traffic manager chips, which were not included in the comparison.

The NP-1 does require some external memory chips to hold the lookup tables. This capability is provided by 256 Mbytes of external DRAMs, which should be adequate to support tables with millions of entries -- large enough to support just about any application likely to be encountered, Fruchter claims.

Although the comparison is already highly favorable to EZchip, it is still conservative, in Fruchter's view. It assumes that the CAMs are 100 percent utilized, which is rarely the case, so more will be needed in practice. Also, AMCC's solution will require more CAMs to process layers five through seven; EZchip's does not.

In addition, there are indirect costs. "[The high chip count] increases the cost of the system much more than just the cost of the components," Fruchter says. "You need to lay out the board, route more traces, buy a bigger power supply, allow for more airflow over the board for cooling, and so on."

AMCC, however, says the comparison is "just ridiculous."

"They're comparing yesterday's technology with tomorrow's," says Keith Morris, director of product management for AMCC's switching and network processing group. EZchip has probably used old-generation parts to make the comparison, he contends. CAMs and SRAMs, which are memory technologies, are advancing rapidly in terms of density and cost. Their price and performance are continually improving, as process technologies used to make these chips move to the next-generation.

"When people start to make outlandish claims, it calls into question all the things they say," Morris carps, adding that if it were all it's cracked up to be, EZchip would have signed a tier-one customer by now, not just a small one.

AMCC also emphasises that one of its key strengths is its ability to offer a complete packet processing solution, including network processor, traffic manager, and switch fabric -- which none of the startups, including EZchip, can claim.

— Pauline Rigby, Senior Editor, Light Reading
http://www.lightreading.com
x-man 12/4/2012 | 10:33:09 PM
re: EZchip Sallies Fourth Having worked on the team that created the first 'network processors' prior to the creation of that name at a large tier1, I am always suspect of single-chip NP claims. Lots of very smart guys have worked this problem, and all the successful designs have SRAM and CAM hanging all over them. And these guys claim to do it all in some square milimeters of silicon. So let's see it do ACL, RPF, CAR and MPLS at linerate with a million route table. I'll be happy to congratulate them.
jamesbond 12/4/2012 | 10:33:01 PM
re: EZchip Sallies Fourth Having worked on the team that created the first 'network processors' prior to the creation of that name at a large tier1, I am always suspect of single-chip NP claims. Lots of very smart guys have worked this problem, and all the successful designs have SRAM and CAM hanging all over them. And these guys claim to do it all in some square milimeters of silicon. So let's see it do ACL, RPF, CAR and MPLS at linerate with a million route table. I'll be happy to congratulate them.

-------------------------------

what is RPF, CAR?

what is "million route table"? If you want them
to forward packets based on MPLS, route table
size shouldn't matter. In fact plain IPv4 forwarding (RFC1812 compliant) with ACLs should be tough enough test.
jamesbond 12/4/2012 | 10:33:00 PM
re: EZchip Sallies Fourth Having worked on the team that created the first 'network processors' prior to the creation of that name at a large tier1, I am always suspect of single-chip NP claims. Lots of very smart guys have worked this problem, and all the successful designs have SRAM and CAM hanging all over them. And these guys claim to do it all in some square milimeters of silicon. So let's see it do ACL, RPF, CAR and MPLS at linerate with a million route table. I'll be happy to congratulate them.

-------------------------------

what is RPF, CAR?

what is "million route table"? If you want them
to forward packets based on MPLS, route table
size shouldn't matter. In fact plain IPv4 forwarding (RFC1812 compliant) with ACLs should be tough enough test.

pablo 12/4/2012 | 10:32:58 PM
re: EZchip Sallies Fourth RPF: reverse path forwarding, a security feature
CAR: committed access rate, SLA requirement

MPLS does require large forwarding tables. Potentially very large ones. For service providers' operations' staff sake, I hope we don't need a million of them, but you never know, and it's a good extreme test case for all carrier protocols these days.

But definitely, IPv4 with ACLs is a tough enough test.

I am sceptical as to the first generation of 10G NPUs being able to live up to all these top high end test cases, but nevertheless what they do deliver is very promising and valuable in itself. While programming them surely will have its challenges, the alternative (design your own in-house 10G capable ASICs) isn't a piece of cake, either.
fantomas 12/4/2012 | 10:32:54 PM
re: EZchip Sallies Fourth Maybe one needs a million entry route table for a core router but definitely not for an edge device.

But routers arent the only products. There are firewalls, Intrusion Detection Systems, Load Balancers (Web Swith) and they dont need million entries.

So yes maybe for a backbone core router, they are not the best solution, but for all the others perhaps they have an edge.
Pauline Rigby 12/4/2012 | 10:32:20 PM
re: EZchip Sallies Fourth I heard back from AMCC, so have added its comments to the story.

[email protected]
silly_valley_boy 12/4/2012 | 10:31:56 PM
re: EZchip Sallies Fourth Would they return your calls for comment? They're another single chip wonder story as well.

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