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Terago Springs a Surprise

Light Reading
News Analysis
Light Reading
1/28/2002

Plenty of companies say they’re in the lead in developing 10-gigabit network processors -- off-the-shelf, programmable chips for making high-performance packet processing gear -- but none has been able to match the claim that Terago Communications Inc. plans to make today (see Terago Rends the Veil).

Terago, a startup that has until now kept a very low profile, plans to tell the world that it’s already shipping its 10-gig network processor. In other words, it’s actually delivering the goods, rather than making promises about what it might be able to do one day -- and that’s likely to go down particularly well with potential customers.

Why? Because the existing lineup of network processor developers has got a pretty poor track record of promising a lot and delivering a little, according to Terago’s founder and CEO Hemant Trivedi. "It is better to first get a working 10-gig part, rather than preannounce and then have to explain why it was delayed," he says. "We think that creates a whole new credibility for the company.

"As soon as we started shipping samples, interest went through the roof," Trivedi adds. "When real silicon is shown, very rarely do you have people asking how many [microprocessor] cores you put in. Instead they say 'Here's my application. Can you show me how to do that?' It takes the conversation up a level."

All the same, Trivedi must have waited a long time for this moment. He says Terago's work goes back five years to 1996, when he and his cofounders worked at a startup called NeoNetworks. NeoNetworks was developing a core router in the same vein as Foundry Networks Inc. (Nasdaq: FDRY) and Nexabit (a startup acquired by Lucent Technologies Inc. [NYSE: LU] in July 1999). In late 1999, its VCs -- Charter Venture Capital and Signal Lake Ventures -- decided to transform the company into Terago and change its focus.

Terago's origin as a systems company may have given it a better insight into what systems vendors want. And it's concentrating on delivering two things: making the software environment easy to use, and having wirespeed performance at all times (for functions at Layers 2 to 4).

The software environment that Terago has developed merits attention. Rather than requiring the user to program the chip in assembly code or C or any proprietary language, the company has developed a graphical user interface (GUI) that customers use to describe their application. A code generator then creates the code automatically.

The advantage of this is twofold, says Trivedi. First, it shortens the time to market, because customers don't have to optimize code in each iteration of the design cycle. And second, it creates uniformity, so customers know what they are going to get in terms of performance. Standard compiler/debugger software environments can yield different results, he notes, depending on the skill of the programmer.

He suggests that Terago's approach to software is unique, although, coincidentally, another startup, Teja Technologies Inc., which is announcing $12 million in funding today, also offers a GUI and a code generator for network processors (see Teja Takes in $12M). Both companies seem blissfully unaware of each other's existence.

Terago says it started shipping samples of its proNP5010 NPU in December 2001. It is planning to release a traffic manager later in the year, along with coprocessors that provide interfaces for aggregation of lower-speed channels.

Its closest competitors in the 10-gig space are probably Agere Systems (NYSE: AGR), Applied Micro Circuits Corp. (AMCC) (Nasdaq: AMCC), and EZchip Technologies (see OC192 Processors: Who's First? and 10-Gig Processors Shape Up). But the way things are going, it wouldn't be much of a surprise to discover yet another stealthy startup whose product development is as advanced as Terago.

— Pauline Rigby, Senior Editor, Light Reading
http://www.lightreading.com

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skeptic
skeptic
12/4/2012 | 11:01:13 PM
re: Terago Springs a Surprise
The software environment that Terago has developed merits attention. Rather than requiring the user to program the chip in assembly code or C or any proprietary language, the company has developed a graphical user interface (GUI) that customers use to describe their application. A code generator then creates the code automatically.
----------------------

Something doesn't sound right here. The only
reason I can think of for a GUI is that whats
underneath the GUI is very difficult to use.
Packet processing code requires a tremendous
focus on optimization and lots of detail about
the "real hardware". Something just sounds
wrong about trying to abstract it away into
a GUI.

somms
somms
12/4/2012 | 11:01:12 PM
re: Terago Springs a Surprise
it is better to have a programmable NP, even if it is painful to program, rather than a "configurable" ASIC that requires "forklift" replacement of the NIC when the customer wants new protocol processing features.
edgecore
edgecore
12/4/2012 | 11:01:12 PM
re: Terago Springs a Surprise

Good article, but a few questions that OEM's might really care about:

What Operating Systems does it support?

Does it have a 32 bit core on the NPU to communicate with the main control plane engine, if not how does it do that?

What protocol stacks has it been tested with (Netplane, IP Infusion, DCL, WIND Net)?

Is this an L2-L4 NPU or does it do up to L7?

You also never mention Marvell's newly announced Prestera chip, its an L2-L4 10 Gig switch procesor, that is "configurable" vs "programable", i.e. they have taken their ASIC expertise and done the optimizations for the customer already!

EC
Pauline Rigby
Pauline Rigby
12/4/2012 | 11:01:11 PM
re: Terago Springs a Surprise
One of these questions was answered in the article. It's a L2-L4 NPU.

Terago told me that handling L4-L7 in the data path was inefficient, since you don't want to do heavy lifting on every packet. Better to offload those kind of things to co-processors.

In any case, Terago says that no customers have asked for L7 processing at 10-gig. People who do L7 stuff do it at the edge, where there are lower speed channels.

As for the other questions, I'll step aside and let Terago answer that itself, if it can be persuaded to come to the message boards.

[email protected]
edgecore
edgecore
12/4/2012 | 11:01:10 PM
re: Terago Springs a Surprise
Why would they openly say "we are not suited for L7", great to see a startup reduce their potential market out of the gate...its not time to be picky or honets :-)

Instead, why not say something more strategic and intelligent such as "We have partnerships with companies such as Solidum to help our L7 OEM's achieve optimal flow classification before getting to our NPU"!

EC
Pauline Rigby
Pauline Rigby
12/4/2012 | 11:01:09 PM
re: Terago Springs a Surprise
Why would they openly say "we are not suited for L7", great to see a startup reduce their potential market out of the gate...its not time to be picky or honets :-)

Instead, why not say something more strategic and intelligent such as "We have partnerships with companies such as Solidum to help our L7 OEM's achieve optimal flow classification before getting to our NPU"!

EC
--------------------

It's my emphasis, not theirs. And I'm not trying to sell anything.

I think they were making the point that if you want to do L7, then go buy a coprocessor because the overall solution will be much higher performance.

[email protected]
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