Startup Spins Novel Network Processor

Interesting network processor architecture, pity about the company name.

That pretty much sums up Cognigine Inc., a startup that today announced additional funding of $10.5 million (see Cognigine Gets Another $10 Million).

Cognigine (pronounced cog-ni-jine) is working on a full-duplex OC192 (10 Gbit/s) network processor, a chip that sits in switches and routers, reading the headers of incoming data packets to figure out how they should be handled.

The startup reckons it's hit on an architecture that will enable it to deliver the first widget of this sort to support OC192 line rates and operate at wire speed.

Of course, plenty of other developers of network procesors are claiming that they'll be able to achieve similar, or even substantially higher speeds sooner or later (see, for instance, Swedes Claim Processor Advance). But all of them, including Cogingine, have yet to ship their chips and prove that they can actually deliver on their promises.

In Cognigine's case, the company hopes to announce product details in December and start shipments early next year, if everything goes according to plan.

Cogningigne claims big savings in real estate by offering full packet processing functionality on a single chip. In contrast, many network processor vendors today are opting for multichip solutions. They offload well-defined functions like packet classification and traffic management onto separate, hardwired chips, freeing up the power of the network processor to do the more complicated tasks.

This isn't the right way to go, because it sacrifices programmability, asserts Nick Kucharewski, the startup's president and CEO. And, of course, it requires more board space.

In addition, Conganignie's claiming that it can process packets in fewer clock cycles than other types of network processor. That's an important factor in achieving wire-speed performance, says Kucharewski.

How is this done? According to Kucharewski, the key is a "distributed microprocessor architecture". The network processor chip is composed of multiple processor cores -- 16, in fact -- connected by a switch fabric. Rather than have each processor core processing a single packet from start to finish, a single task is handled by several processor cores simultaneously. It's possible to do this by dividing up each task into more basic operations.

What's more, Congnognagong's come up with a way of allowing one processor core to handle more than one operation at once. It does this by allowing operations on small pieces of data (8, 16, or 32 bits) to be concatenated to fill the 64-bit-wide data path. As a result, a single processor core can do up to eight operations per clock cycle.

The architecture was invented by company CTO Rupan Roy, who used to develop graphic accelerator chips (which also use parallel processing technology) at Chips & Technologies, a company bought by Intel Corp. (Nasdaq: INTC) -- giving Cogmenahamenahamena something in common with ClearSpeed Technology Ltd.. Clearspeed also started out making graphic accelerator chips and then decided network processors were a better bet (see All Change at Clearspeed ).

However, the architecture is not without its downside. The instruction set that controls the way operations are shared out among the processor cores is very complicated. To hide this complexity from the user, the company added another level to the architecture, translating from one level to the other via an on-chip "dictionary" lookup.

That will make the chip harder to debug, reckons Steve Bassett, senior manager for network processors at Vitesse Semiconductor Corp. (Nasdaq: VTSS).

Bill Klein, network processor product manager at Agere Systems (NYSE: AGR), thinks the complexity of the underlying instruction set could be the product's undoing. "It looks impressive, but putting down multiple engines and trying to schedule them is a very difficult thing," he says.

Even if the new chip performs, it's going to have its work cut out for it, competing against the internal ASIC development groups of system vendors, as well as regular chip makers like Agere and Vitesse.

Cognigine's venture capital funding came from Draper Fisher Jurvetson, Lucent Venture Partners Inc., Wasserstein Ventures, and others. The $10.5 million total announced in today's press release includes $2.5 million in lease financing from Costella Kirsch Inc.

— Pauline Rigby, Senior Editor, Light Reading
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Pauline Rigby 12/4/2012 | 7:41:04 PM
re: Startup Spins Novel Network Processor >It strikes me there are two degrees of SIMD: >Over multiple processor cores, with each core >handling one set of data or a single processor >core handling multiple sets of data (what >Cognigine does) Are both old hat?

yes and no.

SIMD is old hat, but useful. MIMD is old hat, but useful. There are lots of ways of organising parallel computation. Many of these ways can be
mixed to form 'new' cocktails.

Example: if you have a MIMD machine (C-Port's C-5 is an example, although they might not think of it as that) then the step to having each processor include SIMD instructions is not a giant jump. Voila - a MIMD machine with SIMD capabilities.

Now is Cognigine's stuff new? It all depends on labelling. Your description of its machinery made it sound "just like" a C5 but with two differences

- the C5 uses a hierarchy of buses to connect up its 16 processors, while the Cognigine's machinery is said to have a 'switch fabric' connecting the processors
- the C5 processors are more or less MIPS architecture subsets and don't have any SIMD operations (this second claim is from fallible memory)

How do you tell the difference between a hierarchy of buses and a 'switch fabric'? As far as the connected processors and the software that runs on them are concerned, you may not be able to see much of a difference at all.

But quite often companies spin some wondrous architecture story dripping with exotic claims hoping to get attention, when what really matters is
- can I turn this into a product which works better than the other guy's?
- is this stuff an unfair long-term advantage or just a side effect of this generation's environment (data rates, technology, or whatever)

My bitching about Cognigine's bullshit doesn't affect whether or not their product works. It's well known in the network processor world that
if you're building a distributed processor-based network processor, you have two major ways of organising how the processors do the work. One is
- loosely - give each packet to a processor, and have lots of processors work on lots of packets simultaneously. The other is to pipeline a packet
through multiple processors so each processor does a bit of the work needed by each packet. The C-Port C5 chooses the first way; Cognigine says it's doing the latter. The technical differences between the two approaches (which can also be cocktailed, of course) come down to how often a processor has to stop doing current work and start on something new; and how often processors have to send data to another processor. Both activities take some time; the lowest overhead in principle is the CPort approach - a processor changes its workload as rarely as possible (at the end of the packet). But that's just in principle; no reason why Cognigine's machinery couldn't be made to work as well in practice.

So - is their stuff a true piece of novelty? Probably no. Does this make it Bad Stuff? Heck, no. Does it say anything about the utility and
competitiveness of their product? Definitely no.

Remember, you don't need novelty to succeed. Look at Transmeta: a massive PR success based on hype. Underneath the hype was some extremely good engineering and hard work rather than anything truly new, but the hype is what made it possible for the work to get into the world. But Dave Ditzel's better at generating robust hype than the Cognigine folk....
Pauline Rigby 12/4/2012 | 7:41:04 PM
re: Startup Spins Novel Network Processor >Please would you explain what SIMD stands for, who invented it, and how >commonly it's used?

Sure, if non-exhaustively. SIMD = "single instruction, multiple data". It means just what you say - one instruction causes multiple operations to happen in parallel. It's one way of organising a parallel computer ; another is MIMD (multiple instructions, multiple data - generally meaning several different processors each xecuting its own instructions, all connected up somehow).

I cannot dig out (this is pre-coffee) from my mind the exact origins of the classifications, but since they're well-enough known in the microprocessor, DSP and 'media processor' fields, you don't need to do the digging.

SIMD has been used in DSPs (digital signal processors), media processors, and microprocessors for quite a few years. Processor architectures get a few instructions added - generally doesn't cost much silicon and the results can be serious performance improvements on some problems.

Processors which include SIMD extensions include Intel's x86 family ("MMX"), Motorola/IBM's PowerPC ("AltiVec") plus others I'm too foggy to
recall (still before coffee)

Hope this helps enough - as I said, this is all known science so no need to get too exhaustive
>PS, I wish it had been an earlier draft that got posted by accident. It looks like an all-time low in my writing career.

yeah, but that's just a retrospective view., there's always the future :-)

Pauline Rigby 12/4/2012 | 7:41:04 PM
re: Startup Spins Novel Network Processor A net processor engineer and I had a discussion that I thought we should share:

>And although it's hard sometimes to distinguish >between good honest fun, poor reporting and >quotations from the misguided, it is at best >misleading to make it sound ("What's more, >Congnognagong's come up with a way of allowing >one microprocessor to handle more than one >operation at once. It does this by allowing >operations on small pieces of data (8, 16, or 32 >bits) to be cognacatenated to fill the 64-bit->wide data path. As a result, a single processor >core can do up to eight operations per clock >cycle.") as though Cxxxx has invented SIMD >rather than just plagiarised.
>Oh well. maybe it was just an early draft that >got posted by accident?

xinant 12/4/2012 | 7:54:10 PM
re: Startup Spins Novel Network Processor In general it is right.

However, in reality `good' software development
environment will come out at least one year later
after the chip. Look at Intel' 1200 NPU, their
C compiler has not come out yet :(

Basides, providing a paralleling C compiler is
much hard than having a LISP-like compiler. I guess
many NPU companies know how to build the chips, but
I am not sure whether they know how to build a software IDE.
xinant 12/4/2012 | 7:54:11 PM
re: Startup Spins Novel Network Processor Why did you guys talk about C-port and Agree etc.

This is a article about the Cognigine. Any comments on its architecture?

skeptic 12/4/2012 | 7:54:58 PM
re: Startup Spins Novel Network Processor 3) Sitera did not downgrade their chip (nor did C-Port for that matter) to 1.25G; what we've seen is that they are capable only of processing a Gigabit Ethernet flow.

If you are claiming that Sitera can only do
Gigabit Ethernet flows, you are wrong.
lorihiga 12/4/2012 | 7:54:58 PM
re: Startup Spins Novel Network Processor 1) We said that C-Port was acquired by Motorola and that Sitera was acquired by Vitesse. Article says Sitera bought C-Port and then Vitesse
bought Sitera??

2. Some other vendors with slideware produced parts but none of them can doOC-48. Article says none of them produced parts.

3) Sitera did not downgrade their chip (nor did C-Port for that matter) to 1.25G; what we've seen is that they are capable only of processing a Gigabit Ethernet flow.

Lori Higa, senior media relations manager, Silicon Valley
Agere Systems
somms 12/4/2012 | 7:55:03 PM
re: Startup Spins Novel Network Processor .........no need to be a smart-ass...
..the article ORIGINALLY said that
C-Port was bought by Sitera. They corrected it
after my post.
blosox 12/4/2012 | 7:55:15 PM
re: Startup Spins Novel Network Processor "A lot of startups have excellent hardware," says Steve Barnett from Vitesse's network processor group. "But it's not surrounded by all the other things you need, like a software development environment, debugging tools, documentation, training manuals, and the rest. There's a whole lot of deliverables, not just chips."

Probably one of the most experienced and realistic comments ever uttered.

Spot on Mr. Barnett.

Joeboo 12/4/2012 | 7:55:17 PM
re: Startup Spins Novel Network Processor Brilliant deduction. That's probably why the article says:
"C-Port, a startup bought by Motorola Inc. (NYSE: MOT - message board), tried to do something similar at OC48 (2.5 Gbit/s) and failed, he notes. In the end, Motorola had to downgrade the chip to 1.25 Gbit/s."
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