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Optical/IP

Sources: Cisco Eyes TCAM Startup

Cisco Systems Inc. (Nasdaq: CSCO) is close to acquiring little-known startup Spans Logic Inc. , sources say, a deal that could put some pressure on chip vendor NetLogic Microsystems Inc. (Nasdaq: NETL).

Still in stealth mode, Spans Logic is widely believed to be building ternary content-addressible memories (TCAMs) -- chips designed for the complex table searches performed by IP routers. Sources around the chip industry say Spans Logic's goal was to develop a cheaper TCAM, one built from commodity memory.

TCAMs were championed by Cisco in the 90s, and Cisco remains the largest customer for the parts. "You can't last long in that business if you don't have that customer," says once source in the chip industry.

It's not surprising, then, that Cisco would want TCAMs of its own. One source believes Cisco intends to integrate Spans Logic's TCAM into Cisco ASICs; another says Cisco has told its chip suppliers to begin interoperability tests with Spans Logic.

Cisco declined to comment; Spans Logic did not return a call for comment.

Should the acquisition go through, it probably wouldn't be pricey. Spans Logic has raised just one funding round of $6 million, according to a 2005 San Jose Mercury News survey. Spans Logic's spartan Website lists ATA Ventures and Crescendo Ventures as investors.

One chip industry source, though, says Spans Logic's primary investor is Cisco itself. The deal, then, would be akin to a spin-in, with Cisco intending all along to acquire the startup if the technology worked out. It wouldn't be the first time Cisco tried something like that. (See Andiamo Crew Reunites With Cisco.)

The source estimate's Spans Logic's headcount at "between 15 and 30" and notes that the startup has yet to collect any revenues.

Cisco buys TCAMs from Integrated Device Technology Inc. (IDT) (Nasdaq: IDTI) and NetLogic, but the latter would appear to have more to lose. NetLogic is said to be Cisco's primary TCAM supplier, and it gets more than 60 percent of its revenues from Cisco. IDT, meanwhile, is a Silicon Valley old-timer that sells a range of other chips to other companies, although Cisco has accounted for more than 20 percent of its revenues during each of the last three years.

But one chip industry source believes Spans Logic is targeting too low-end a niche to harm NetLogic. NetLogic's specialty is in higher-end systems that require TCAMs too sophisticated to be integrated into ASICs, whereas Spans Logic has been targeting a design for lower-end equipment, the source says.

NetLogic does have low-end chips, but those parts don't sell into Cisco, the source says.

NetLogic declined to comment.

That Cisco might look for TCAM alternatives isn't surprising. The company supposedly has asked Japanese firm Renesas Technology Corp. , a spinoff of Hitachi Ltd. (NYSE: HIT; Paris: PHA), to consider building TCAM cores for use inside ASICs. Asked about Renesas on earnings calls, NetLogic officials have said they aren't seeing any direct competition from the company.

— Craig Matsumoto, West Coast Editor, Light Reading

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materialgirl 12/5/2012 | 3:14:19 PM
re: Sources: Cisco Eyes TCAM Startup What is the definition of "low end" and "high end" here? What about the chips makes them different? Why can a "high end" chip not be integrated into as ASIC, especially as geometries fall and gate counts grow?
paolo.franzoi 12/5/2012 | 3:14:19 PM
re: Sources: Cisco Eyes TCAM Startup
Memory structures, included features, size, etc. leading to density and performance issues.

It is not straightforward to include high density memory structures, especially advanced ones, into ASIC designs. The low level elements are different. ASIC structures are generally built up of transistors in a particular manner optimized for logic. High density or High Performance memories build their structures up based on optimization for the memory. Logic suffers in a memory structure, Memory suffers in a logic structure.

So, if you need lots and lots of a particular kind of memory you have to evaluate whether having it in a separate device is better than having it integrated. This is very similar to tradeoffs carriers make about whether they want to integrate two existing products or not. Generally, integration leads to compromise.

seven
paolo.franzoi 12/5/2012 | 3:14:16 PM
re: Sources: Cisco Eyes TCAM Startup
Sigint,

There are CAMs of various types available as macros. The efficiency might be 50% compared to SRAM, I am not sure with TCAMs in this particular case. So, it certainly possible to include some amount on chip.

I was just being clear about the tradeoffs of on chip versus off chip memory in terms of performance, power, and process.

seven
sigint 12/5/2012 | 3:14:16 PM
re: Sources: Cisco Eyes TCAM Startup To add to the previous post, I do realise that TCAM being the power guzzlers they are, would likely complicate thermal design for an already `on-the-edge' chip.

Sigint
sigint 12/5/2012 | 3:14:16 PM
re: Sources: Cisco Eyes TCAM Startup Good post, brook.

One question, if you'd please comment; Regardless of the perils - many networking chips do incorporate vast amount of ram (I haven't seen any TCAM though). These are typically macros supplied by vendors - optimised for a particular process, and don't really need to be synthesised.

Of course, memory in any significant amount tends to dominate the die, and causes tonnes of headaches with yield, not to speak of chewing up precious tester time. However, vendors do incorporate serious memory anyway, how much more difficult would it be to accommodate a macro for TCAM? Especially, of the comparator and priority decoder didn't have to be synthesised? As I understand it, a TCAM would yield about 1/2 the Mbits comapred to SRAM for equivalent acreage.

Thanks,
Sigint
paolo.franzoi 12/5/2012 | 3:14:14 PM
re: Sources: Cisco Eyes TCAM Startup
mg,

As Sigint already noted, there is lots of memory of all kinds on ASIC devices already. So, on the low end side those devices - if not already eaten - will be eaten.

As for the lower geometries, you are hitting a huge tradeoff. At 90nM mask sets alone could run $1M. So, you have to be real sure your device is going to be a volume device to scale down. The other problem you run into is that the semiconductor construction is so different that you will always have an advantage with memory processes for bulk memory. The advantages can be daunting - 50% of area and power in the case of static RAM.

So, I never see the case of "high end" - big or fast - memories going away.

seven
materialgirl 12/5/2012 | 3:14:14 PM
re: Sources: Cisco Eyes TCAM Startup Dera seven:
Thank you for the post. Now, I wonder if this ever ends. Say, at 65nm or at 45nm, do the inefficiencies of combo logic/DRAM chips cease to over-ride system requirements for throughput? Or, say with video growing, is it a never-ending race?
curiousgeorge 12/5/2012 | 3:14:14 PM
re: Sources: Cisco Eyes TCAM Startup Beyond the optimization of yeild and process, there is the consideration of scalability.

Whenever you put memory inside the ASIC chip, you've placed a hard limits on something (RTT, # of MAC addresses, depth of lookup tables, code size) - requires you to guess very well or massively overdesign your chip.

Feeds into the low end / high end discussion. Upperbounds are perfectly acceptable on "low end" applications, and not usually tolerated on "high end".

p.s. CAM cells are fundamentally different, and not a large niche (atleast partly due to folks having figured out a way around doing efficient hash lookups for many cases). In general hard IP is a tough market even for the more basic stuff.
paolo.franzoi 12/5/2012 | 3:14:13 PM
re: Sources: Cisco Eyes TCAM Startup
mg,

I agree with Sigint and curious here. I am hopeful that this fully answers your question.

seven
sigint 12/5/2012 | 3:14:13 PM
re: Sources: Cisco Eyes TCAM Startup curious:
Whenever you put memory inside the ASIC chip, you've placed a hard limits on something (RTT, # of MAC addresses, depth of lookup tables, code size) - requires you to guess very well or massively overdesign your chip.
____________________________________________________

Well, depends. An acceptable practice would be to add an "optimal" amount of internal memory, and allow the connection for external devices as well. That's how most networking silicon would do it. This is advisable for things like TCAM, and probably necessary for packet buffers.

For low end stuff, as you had yourself pointed out, there might be cheaper hash implementations.
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