PMC Offers 'Cerent Chip'

While most of the optical networking industry was preoccupied with the NFOEC last week, PMC-Sierra Inc. (Nasdaq: PMCS) quietly announced a chip set that could turn out to be a significant milestone in the development of metro equipment.

The chip set, called CHESS-Narrowband, gives vendors some off-the-shelf silicon for making switches that can pack thousands of really tiny channels -- the DS0s (64 kbit/s) connections that carry single telephone calls -- into STS1s (51.8 Mbit/s), the smallest-sized pipes in Sonet networks (see PMC-Sierra Offers Grooming Chip Set).

In essence, it gives competitors of Cisco Systems Inc. (Nasdaq: CSCO) an easy way of developing something that’ll go head to head with Cisco’s highly successful ONS 15454, the box developed by Cerent that’s been selling like hot cakes for the past year or so.

Up until recently, Cisco hasn’t faced particularly strong competition in this market. That’s because only a handful of startups went to the trouble of developing their own ASICs application-specific integrated circuits) to do sub STS1 rate grooming. Cerent was one of them. Others included Cyras and Siara, the two startups spun out of Fiberlane together with Cerent, which ended up being bought for billions of dollars by Ciena Corp. (Nasdaq: CIEN) and Redback Networks Inc. (Nasdaq: RBAK), respectively.

Now, PMC-Sierra is paving the way for lot of other vendors to jump on the bandwagon and build ONS 15454 look-alikes and other types of metro equipment with its CHESS-Narrowband chip set.

It’s important to note that this isn’t the first sub-STS1-rate grooming chip, but it appears to be by the far the most powerful to date.

PMC-Sierra itself has long had a puny little thing called the TUDX which can handle a miniscule amount of data -- 311 Mbit/s, to be precise.

More recently, Paxonet Communications Inc. started shipping a sub-STS1 crossconnect that could process a serious amount of data -- 2.5 Gbit/s (see Chip "Could Boost Metro Market").

Now, PMC-Sierra’s new chipset has raised the bar again. It comes in two flavors, 20 Gbit/s or 7.5 Gbit/s, depending on the size and requirements of the equipment. In its 20-Gbit/s incarnation, it can crossconnect 258,048 DS0 channels.

With the details of the silicon already worked out, systems vendors can focus on more worthwhile things, says Steve Perna, VP of PMC-Sierra's optical networking division. "Our customers can concentrate on higher-level processing and offering differentiated services," he says.

Taking the elevator

As usual, the devil is in the details. From a high-level perspective, any form of sub-STS1 grooming is seen to be a Good Thing (in the right application, of course). But it turns out that there is more than one architecture that can be used.

PMC-Sierra's chipset implements centralized grooming. It comes as a two-chip set. One chip sits on the switch card and interfaces to a second chip on the line card. In this architecture, there's no need to do STS1 grooming because it's already taken care of within the sub-STS1 (also called VT-level) fabric.

Other architectures divide the labor between STS1 grooming fabrics and VT grooming chips. There's a good reason for dividing things up this way. STS1 is the "ground floor" of Sonet. To get to higher floors -- OC12 (622 Mbit/s), OC48 (2.5 Gbit/s), and above -- you take one set of elevators. To get to the basement, which is the olde world of PDH (plesiochronous digital hierarchy) signals, you need to take a different elevator. Data rates in Sonet are not exact multiples of the DS0s, DS1s, and so on, that exist in the PDH world, and STS1 is where they come together.

Paxonet says its chip is designed to be used in a distributed architecture like this. Its product is a single chip that fits on the line card. The chip performs VT-rate grooming and then sends the data off to a switch card, which can carry out STS1 grooming as well, if desired.

Different architectures have different applications, says Chetan Sanghvi, Paxonet's CEO. "We believe there's going to be room for both." He adds that Paxonet's chip has a lower density because of the way its designed to be used.

But Sanghvi believes that PMC-Sierra's solution has a fundamental weakness. "It has designed a proprietary bus protocol for the backplane, so to connect to the chip on the switch card, you need an additional chip on the line card. That means you have to buy both chips from PMC-Sierra, and they can't interoperate with other devices." Sanghvi doesn't think that's the right way to go. "There are other more commonly used bus protocols that they could easily have picked."

— Pauline Rigby, Senior Editor, Light Reading
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dietaryfiber 12/4/2012 | 8:04:43 PM
re: PMC Offers 'Cerent Chip' There is a standard for mapping DS0s into STS-1s. This is direct mapping and was intended for SONET when it was going to be a truly Synchronous Network.

DS0s are used for those very useful devices known as telephones.

gardner 12/4/2012 | 8:04:43 PM
re: PMC Offers 'Cerent Chip' A couple of points. Number one, although STS1 is the basic module in SONET, an STS1 payload can be structured to carry VT1.5s (DS1s), thus it isn't really true to say that STS1s are "the smallest-sized pipes in Sonet networks". Number two, although there is a standard mapping to DS1 bit rates in SONET there is none for DS0s (there is no smaller VT than an VT1.5). Although one could extract the DS0s from the DS1 in the VT1.5 it is not something standard to SONET . This would seem to indicate that they are going it alone standards-wise. Comments anyone? (And I would also be anxious to hear of what use it is to a data network to break out such tiny pipes (64Kbps is pretty small)).
Ranger 12/4/2012 | 8:04:41 PM
re: PMC Offers 'Cerent Chip' I'm sure you would be offended it you were labelled as "Lite Wreeding".
Pauline Rigby 12/4/2012 | 8:04:38 PM
re: PMC Offers 'Cerent Chip' A late night editing error. I rushed to fix it this morning.

[email protected]
Peter Heywood 12/4/2012 | 8:04:37 PM
re: PMC Offers 'Cerent Chip' In the cool light of morning, I decided to simplify the front end of this story - get to the point faster and cut out the stuff on the parallels with Ciena's CoreDirector.

For those of you who think you might have missed something, the business of Cerent getting a head start on the competition by developing its own ASICs has a parallel. Lightera did exactly the same thing and that's how Ciena ended up having a big success with the CoreDirector.

In the past few months, a number of chip vendors have brought out merchant silicon that's enabling folk like Sycamore and Nortel to get started on trying to catch up with Ciena.

So this now also has a parallel in the metro market, with PMC Sierra and Paxonet announcing Cerent type chips.

glowingduck 12/4/2012 | 8:04:33 PM
re: PMC Offers 'Cerent Chip' I thought the same thing: why a DS0 (64 k) cross-connect fabric? Sure the 454 doesn't have a DS0 fabric, but fully-featured narrowband DCSs with SONET interfaces, in all shapes and sizes, have been around for years, AND they are cheap and plentiful. Any narrowband DCSs vendor will make you a DEAL today!

Is there a real market for this new chipset?

ivehadit 12/4/2012 | 8:04:32 PM
re: PMC Offers 'Cerent Chip' peter,
you're creating unneccessary confusion for need of a catchy headline. cerent doesn't do ds0 processing, and neither do any cerent lookalikes plan on that.

even circuit switches now have sts-1 interfaces, however they need to break the signal down to ds0 before they can do the switching. is the application for this a circuit switch lookalike? or, ds0 crossconnects that sit in front of circuit switches to groom traffic into a circuit switch. perhaps ds0 frame relay circuits, is there anyone from pmc on this board that can clarify the true application?
lighthearted1 12/4/2012 | 8:04:32 PM
re: PMC Offers 'Cerent Chip' Is it possible that Astral Point and Mayan have proven that no one really cares about getting to the DS0 level within an edge/core box. They touted 3/1/0/ capability, but no takers.

The question that seems to come up most often is -
Do you dilute the cost of a high speed interface slot by using it for low speed applications?

In most cases it is simply cheaper to buy a managed, external 3/1/0 mux and use your high priced, multiservice chassis for the good stuff.
kww 12/4/2012 | 8:04:31 PM
re: PMC Offers 'Cerent Chip' I think that people will find that feature useful now that the mania for delivering 10GigE pipes to every home while losing billions in the process has calmed down.
The real problem with PMC's offering is that their "DS0 switching" feature is a sham. It requires byte-synchronous mapping of DS1 traffic before DS0 switching can work. Byte-synchronous mapping is so rare that the feature is virtually useless.
gardner 12/4/2012 | 8:04:28 PM
re: PMC Offers 'Cerent Chip' There is a standard for mapping DS0s into STS-1s.

And what would that standard be? GR-253CORE? I don't think so. Look for yourself. Here is what GR-253CORE says: "The VT structure is designed for transport and switching of sub-STSGÇô1 rate payloads. There are four sizes of VTs: VT1.5 (1.728 Mb/s), VT2 (2.304 Mb/s), VT3 (3.456 Mb/s), and VT6 (6.912 Mb/s)." Do you see 64Kb/s in that list? I didn't think so.

This is direct mapping and was intended for SONET when it was going to be a truly Synchronous Network.

Merely asserting there must be one doesn't cut it. Prove it by citing it chapter and verse. And while you are at it explain what you mean by "when it [SONET] was going to be a truly Synchronous Network".

DS0s are used for those very useful devices known as telephones.

This kind of flippancy doesn't improve your argument. Will I see you post here to tell me what standard defines a DS0 container for SONET or will you just slink away into the night like a smart aleck kid should?
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