PMC Offers 'Cerent Chip'
While most of the optical networking industry was preoccupied with the NFOEC last week, PMC-Sierra Inc. (Nasdaq: PMCS) quietly announced a chip set that could turn out to be a significant milestone in the development of metro equipment.
The chip set, called CHESS-Narrowband, gives vendors some off-the-shelf silicon for making switches that can pack thousands of really tiny channels -- the DS0s (64 kbit/s) connections that carry single telephone calls -- into STS1s (51.8 Mbit/s), the smallest-sized pipes in Sonet networks (see PMC-Sierra Offers Grooming Chip Set).
In essence, it gives competitors of Cisco Systems Inc. (Nasdaq: CSCO) an easy way of developing something that’ll go head to head with Cisco’s highly successful ONS 15454, the box developed by Cerent that’s been selling like hot cakes for the past year or so.
Up until recently, Cisco hasn’t faced particularly strong competition in this market. That’s because only a handful of startups went to the trouble of developing their own ASICs application-specific integrated circuits) to do sub STS1 rate grooming. Cerent was one of them. Others included Cyras and Siara, the two startups spun out of Fiberlane together with Cerent, which ended up being bought for billions of dollars by Ciena Corp. (Nasdaq: CIEN) and Redback Networks Inc. (Nasdaq: RBAK), respectively.
Now, PMC-Sierra is paving the way for lot of other vendors to jump on the bandwagon and build ONS 15454 look-alikes and other types of metro equipment with its CHESS-Narrowband chip set.
It’s important to note that this isn’t the first sub-STS1-rate grooming chip, but it appears to be by the far the most powerful to date.
PMC-Sierra itself has long had a puny little thing called the TUDX which can handle a miniscule amount of data -- 311 Mbit/s, to be precise.
More recently, Paxonet Communications Inc. started shipping a sub-STS1 crossconnect that could process a serious amount of data -- 2.5 Gbit/s (see Chip "Could Boost Metro Market").
Now, PMC-Sierra’s new chipset has raised the bar again. It comes in two flavors, 20 Gbit/s or 7.5 Gbit/s, depending on the size and requirements of the equipment. In its 20-Gbit/s incarnation, it can crossconnect 258,048 DS0 channels.
With the details of the silicon already worked out, systems vendors can focus on more worthwhile things, says Steve Perna, VP of PMC-Sierra's optical networking division. "Our customers can concentrate on higher-level processing and offering differentiated services," he says.
Taking the elevator
As usual, the devil is in the details. From a high-level perspective, any form of sub-STS1 grooming is seen to be a Good Thing (in the right application, of course). But it turns out that there is more than one architecture that can be used.
PMC-Sierra's chipset implements centralized grooming. It comes as a two-chip set. One chip sits on the switch card and interfaces to a second chip on the line card. In this architecture, there's no need to do STS1 grooming because it's already taken care of within the sub-STS1 (also called VT-level) fabric.
Other architectures divide the labor between STS1 grooming fabrics and VT grooming chips. There's a good reason for dividing things up this way. STS1 is the "ground floor" of Sonet. To get to higher floors -- OC12 (622 Mbit/s), OC48 (2.5 Gbit/s), and above -- you take one set of elevators. To get to the basement, which is the olde world of PDH (plesiochronous digital hierarchy) signals, you need to take a different elevator. Data rates in Sonet are not exact multiples of the DS0s, DS1s, and so on, that exist in the PDH world, and STS1 is where they come together.
Paxonet says its chip is designed to be used in a distributed architecture like this. Its product is a single chip that fits on the line card. The chip performs VT-rate grooming and then sends the data off to a switch card, which can carry out STS1 grooming as well, if desired.
Different architectures have different applications, says Chetan Sanghvi, Paxonet's CEO. "We believe there's going to be room for both." He adds that Paxonet's chip has a lower density because of the way its designed to be used.
But Sanghvi believes that PMC-Sierra's solution has a fundamental weakness. "It has designed a proprietary bus protocol for the backplane, so to connect to the chip on the switch card, you need an additional chip on the line card. That means you have to buy both chips from PMC-Sierra, and they can't interoperate with other devices." Sanghvi doesn't think that's the right way to go. "There are other more commonly used bus protocols that they could easily have picked."
— Pauline Rigby, Senior Editor, Light Reading