Based in St. Louis, of all places, Erlang has been NEC Electronics Corp.'s baby until now, with the Japanese firm footing all of Erlang's Series A and B rounds, for undisclosed sums (see NEC Partners with Erlang Technology). Analysts expected NEC Electronics to acquire Erlang, but the larger firm's sagging financial situation since the spinout made that impossible.
Against this background, Erlang instead hit the pavement for more funds. Series C, which closed earlier this month, introduced venture capital firms into the mix, although NEC remains the largest investor. The round was led by a Silicon Valley firm and included overseas investors; Erlang won't reveal the investors' identities until next month, says Paul Min, Erlang's CEO.
"The syndication process was hard. It's one thing to find a VC interested and another to get several VCs together," Min adds.
It's important to note that Erlang's investor is NEC Electronics, not the conglomerate NEC Corp. (Nasdaq: NIPNY). The electronics arm spun out in November and is now an independent company with an initial public offering in the works, according to Min.
This explains why Mindspeed Technologies, not Erlang, won a recent switch-fabric contract with the larger NEC (see Mindspeed Switch Fabric Lives On). NEC Corp.'s networking division has a relationship with Mindspeed that predates Erlang, Min says -- but he adds that Erlang is gunning to displace that Mindspeed win.
The Series C closing is important as Erlang prepares to launch its ENETXe product line this year. Chances are, the launch wouldn't take place if the money wasn't in hand, says Jag Bolaria, analyst with consultancy The Linley Group.
"A lot of fabric vendors' schedules are dictated by how much money they have, so I wouldn't be surprised if the Xe was pushed out because they didn't have their financing all lined up," he says.
With the Xe's release, here's how Erlang's product portfolio shapes up.
- The ENETSe has been shipping for more than a year but can handle only 40 Gbit/s of full-duplex traffic (that is, 40 Gbit/s in and 40 Gbit/s out simultaneously).
- The ENETXe, which will cover the ground from 80 Gbit/s to 640 Gbit/s full-duplex, is due to ship to beta customers in "February or March," Min says.
- A follow-up version of the Xe, capable of switching 2.5 Tbit/s full-duplex, should arrive sometime in the second quarter. Min admits this might be overkill for the current market. "I don't know if anybody's going to buy this, but we have it!" he says. "Especially in the overseas market, 640 [Gbit/s] covers 99 percent of the opportunity."
- An even larger switch fabric, the ENETTe, has been shelved for now -- not surprising, considering the bleak market for the core routers it was intended to serve (see Pluris Shutdown Confirmed).
Erlang also developed its own traffic manager, an adjunct chip that's becoming accepted as a means of preserving QOS in high-speed systems (see Traffic Manager Chips). The traffic manager is available in FPGA (field programmable gate array) form now and could be spun into an ASIC (application specific integrated circuit) for higher-volume customers, Min says.
Erlang didn't really consider acquiring a traffic manager from another company, because its architecture is too unusual (see below). Besides, Min jokes, "Who wants to be bought by a company in St. Louis?"
There also weren't a lot of choices, to be fair. Aside from Azanda Network Devices' chip, most traffic managers are being developed by companies doing their own switch fabric -- examples being Applied Micro Circuits Corp. (AMCC) (Nasdaq: AMCC), Internet Machines Corp. and ZettaCom Inc. Looking ahead, the company plans to add specialized features to its fabrics, particularly for handling the shifting encryption needs of 3G wireless. Huawei Technologies Co. Ltd. is teaming up with NEC Electronics for 3G work, and Erlang's hoping it can sneak into that project as well, Min says.
Meanwhile, talks of NEC Electronics acquiring Erlang aren't dead, but Min refused to give any details, as NEC Electronics is hoping to go public late next quarter, and he didn't want to violate the quiet period. "We are certainly in their strategic map," he asserts. "Certainly there has been talk, and there will be additional talks."
Under the hood
It's worth taking a minute to peek at Erlang's technology, because it involves an interesting gambit. Erlang's architecture is a shade or two removed from current thinking in switch fabrics.
Most switch fabrics cut up an incoming packet and portion it into fixed-size cells, which makes it easier to schedule their trip across the center of the switch fabric -- there aren't any surprises in terms of how long the trip takes, or how much buffer memory the cell occupies.
Erlang eschews fixed-size cells, a decision intended to accommodate the unpredictable packet sizes of Internet Protocol. It's a nice idea, but it opens the problem of scheduling data streams properly, so that an unexpectedly long packets don't get in each other's way. Erlang handles this by putting the scheduling function into the switching element itself.
No one else seems to take that approach. Most architectures do the scheduling in one chip called an arbiter ("centralized" scheduling), or they delegate scheduling to the line cards ("distributed" scheduling). Either way, the packet's destination port is chosen before it traverses the crossbar -- the chip, usually residing on its own card, that connects all possible ingress and egress ports.
Erlang makes the decision at the last minute. The intersection points inside its crossbar hold the scheduling intelligence, and they decide on the fly where a particular packet should go. Packets belonging to one data stream are sent to the same destination, usually, and the architecture is smart enough to know which egress ports are available and which aren't.
That's nice, but it's got two problems, says Linley's Bolaria. First, cell-based switching is so common that many network processors and corresponding ASICs already do the segmenting of packets into cells -- meaning Erlang doesn't have to do all that work to handle variable-length packets. "If you have an NPU already doing the SAR'ing [segmentation and reassembly], that kind of neutralizes the benefit," he says.
Second, the Xe requires too many chips. To achieve 640 Gbit/s requires a three-staged array of Xe chips, as opposed to the single chip that OEMs would prefer.
"If you're doing high-capacity, then you're going to use a lot more chips with these guys," Bolaria says. "They're a stage away from having the right product."
The chip count should drop as the Xe design goes through the normal revisions. Given the continued backing of NEC and the recently-raised money, Bolaria is confident that the company has bought enough time to give its technology a chance. "Erlang's definitely one of the companies who [will] stay around to do a second generation," he says.
— Craig Matsumoto, Senior Editor, Light Reading