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Optical/IP

Bay's ATM Chip Heads Into Battle

An obsession with technology is about to pay off for network processor vendor Bay Microsystems Inc., which has scored an unusual design win with the U.S. government.

Bay and its competitors tend to sell to equipment makers, not to network owners directly. But Hank Dardy, chief technical adviser for IT and computation at the U.S. Naval Research Labs, liked the fact that Bay's Montego chip incorporated a component called a SAR (Segmentation and Reassembly), something that's still a relative rarity at OC192 speeds.

The SAR isn't really as painful as it sounds. Basically, it helps take apart or put together ATM traffic streams. So it's required on either end of a transmision line. Bay's integrated network processor and high-speed SAR put it in an elite category of bulked-up, ATM-ready network chips.

The government's users -- including the Department of Defense and other agencies that Chuck Gershman, Bay CEO, was skittish about naming [ed. note: they'd have to kill him?] -- are on an ATM network that's being upgraded to OC192. Rather than switch to something like Internet Protocol (IP), the government is sticking with ATM, having enlisted General Dynamics Corp. to craft a proprietary security chip for ATM that handles encryption purely at Layer 1.

"They said they had been looking for something like this for the better part of a year. They were thinking it didn't exist," says Gershman.

Dardy confirms that he had been seeking the necessary pieces of the OC192 network. He also says that, while some companies -- like Cisco Systems Inc. (Nasdaq: CSCO) -- have their own ATM SARs at that speed, it appears no merchant chips other than Bay's fit the task.

Most network processors claim to have ATM support, but Bay looks to be on the cutting edge of OC192 capabilities. "Out of all of them, Bay has a very strong solution," says John Metz, president of consulting firm Metz International.

If Montego really is that good, it's because Bay emphasized ATM from the start, having never believed in the all-IP network. While most network processors were engineered with Internet Protocol in mind, Bay chose an approach that concentrated on multiservice networks and the existing ATM infrastructure.

"We just saw that this other model was there," Gershman says. No other network processor company seemed interested in ATM, except for Agere Systems (NYSE: AGR/A) -- the spinoff from Lucent Technologies Inc. (NYSE: LU) (see Lucent Christens Its Spinoff).

Given its goals, Bay needed to build a processor that could handle massively channelized traffic while keeping ATM circuits intact. As a result, Montego juggles thousands of queues based on destination. In contrast, Gershman says, an IP box might accommodate thousands of microflows but will send traffic to just a handful of "next-step" destinations.

Luckily for Bay, the legacy networks won out over the IP-based CLECs, creating unexpected demand for ATM and even Fibre Channel (see The New Legacy Network). That's brought ATM into the sights of larger network-processor players such as IBM Corp. (NYSE: IBM) (see S3 Adds ATM for IBM)

"Agere was one of the first ones to come out [with ATM support], and that was their strength," Metz says. "Now everybody is gunning for them."

Bay hasn't had an easy time of it. Bay missed its original target of mid-2001 (see Network Processors Proliferate), and the dramatic effort to finish its chip became the subject of a week-long feature series in the San Jose Mercury News. The first samples of Montego finally arrived last March (see Bay Joins the Big Leagues), and Bay was demonstrating OC192 capabilities by May.

Bay's win will also include a set of network-interface cards for connecting supercomputers directly to the ATM network, something that's easily crafted using the startup's existing technology, Gershman says. The government is even interested in seeing what Bay can do at OC768 (40 Gbit/s). "There is a strategic pull in certain organizations to move the technology forward, if you find the right people."

Bay will be giving a hint of its technology at SC2002, the supercomputing conference in Baltimore next week. The startup will be in the Marconi plc (Nasdaq/London: MONI) booth with an elaborate setup connecting SGI supercomputers to a Marconi ATM switch at OC192 speeds.

— Craig Matsumoto, Senior Editor, Light Reading
www.lightreading.com

Want to know more? The big cheeses of the optical networking industry will be discussing multiservice switching at LightSpeed Europe. Check it out at http://www.lightspeedeurope.com.



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mrcasual 12/4/2012 | 9:20:14 PM
re: Bay's ATM Chip Heads Into Battle Point taken. Sorry for the Monday morning grouchiness.

Perhaps I'm a little sensitive here because when I
checked out the Montego datasheet it was very scant
in terms of real details.

If it truly does all that it claims it can do, and
at wire rate no less, then the datasheet should at
least provide a simple interface picture so that
people could do a first pass analysis of the device
to see if they are legit or are blowing smoke like so
many other NPU vendors out there.

The NPU industry suffers, in general, from over hype
by vendors. Many people have been burned by this and
it makes it harder for companies that have products that
actually do what they say they will do.

If Bay's product can do all the things they say it can
do and people are willing to buy it then kudos to them.

But given the general lack of information, I have to
be skeptical. It's not going to hurt them to show their
competitors that they are using 2/4/8/whatever DDR DRAM
busses and 2 QDR SRAM busses. (Just speculation on my
part BTW).

The chip is what it is. Don't try to hide its
warts. Your customers will find out eventually.
CaboSanLucasBoy 12/4/2012 | 9:20:13 PM
re: Bay's ATM Chip Heads Into Battle =================================================
But given the general lack of information, I have to
be skeptical. It's not going to hurt them to show their
competitors that they are using 2/4/8/whatever DDR DRAM
busses and 2 QDR SRAM busses. (Just speculation on my
part BTW).

The chip is what it is. Don't try to hide its
warts. Your customers will find out eventually.
-----------------------------------------------

By talking to someone on the inside, I have confirmed that there is no QDR SRAM. We have someone going to SC2002, I keep you posted on how that goes.

=================================================
If it truly does all that it claims it can do, and
at wire rate no less, then the datasheet should at
least provide a simple interface picture so that
people could do a first pass analysis of the device
to see if they are legit or are blowing smoke like so
many other NPU vendors out there.
-----------------------------------------------

It appears they acheive this by constraining the problem they were trying to solve - namely wirespeed editing (transformation), metering, marking, etc. for layers 2-to-4.

You are correct many vendors seem to be blowing smoke up my harddrive (or somewhere else for that matter) when it comes to what they really can do with their devices. I know someone who was trying to do wire-speed editing and traffic engineering (~8K queues) with software. Needless to say, that vendor is now not used here for NPUs.

I can't agree with you more about over-hype in this industry that's why we're going to see the set-up at SC2002 and if it warrants it we'll go farther. I'll keep you posted.
sgan201 12/4/2012 | 9:20:13 PM
re: Bay's ATM Chip Heads Into Battle Hi Mr. Casual,
Those states are not the major items in AAL5 SARing.. The main thing is that for each VCC, you need to buffer the cells until you receive the last AAL5 cells.. It is the cell buffer that required the largest amount of memory..
Assuming maximum packet size of 65,535 bytes = 64Kilobytes..
Number of connections = 10K
Total RAM for AAL5 SARing buffer = 64K X 10K ~ 640 MBytes..
Normally, you do some level of over-subscription..
128MBytes is probably enough..
Did you really design an AAL5 SARing engine before??
Of course, if you made some assumption about the max AAL5 packet size being smaller, then , you cell buffer will be smaller...
xinant 12/4/2012 | 9:20:12 PM
re: Bay's ATM Chip Heads Into Battle -----------------------------------------------

By talking to someone on the inside, I have confirmed that there is no QDR SRAM. We have someone going to SC2002, I keep you posted on how that goes.

_____________________________________________

This is really a surprise since I have never heard of any other NPU companies did not do that.

Usually SRAM is used for storing the linked list which contains pointers to the payload. SDRAM or DDR is used for storing payload.

If they do not use SRAM, myabe they would use RCMEM or RDMEM. However I doubt whether they can have the same performance.

broadbandboy 12/4/2012 | 9:20:12 PM
re: Bay's ATM Chip Heads Into Battle "If you want to support ABR (Available Bit Rate service), then your estimate is not far off. But if only bare-bones UBR with AAL5 suport is required, then you can get by with much less state memory per VC."

---------------------------

Question - does anybody know for sure if the Bay chip supports just AAL5/UBR traffic, or can they do the full range of ATM QoS - CBR, VBR, UBR, ABR, etc?

BBboy
the_thinker 12/4/2012 | 9:20:11 PM
re: Bay's ATM Chip Heads Into Battle You say "no exotic memory". What does that mean? What memory do you use, and how much?
BayMicroPaul 12/4/2012 | 9:20:11 PM
re: Bay's ATM Chip Heads Into Battle I work for Bay and have been watching this thread with some interest. Some of the posted information is correct and some is incomplete. I am sorry for barging in on a user forum, but just wanted to provide some clarification to information that is already in the public domain.

At the risk of sounding like a commercial...

In response to what the Montego is:
The Montego performs 5 basic functions: (1) Classification, (2) Policy Controls [editing, etc] {note these first two blocks are the usual functionality of a classically defined NPU}, (3) Wire-speed packet/segment SAR [does packets, cells or segments], (4) Robust Queue Manager and (5) Traffic Engineering Manager [TM 4.1 compliant, etc. - QoS with CBR, VBR, UBR, etc.] This is on top on a high-speed switching architecture.

In response to the "smoke up my ...":
The Bay Architecture is deterministic regardless of traffic pattern or operation(s) performed. No statistical multiplexing is necessary to achieve wire-rate.

In response to "RAM types..."
No exotic RAM types are necessary to achieve this performance.

In response to "hiding the warts..."
This is not a "God-chip". It is optimized to process multiservice network traffic at wire-speed. Given that you can't program the device to play blackjack or windows. Bay has nothing to hide, if you're interested we can show you what it can and can't do.

I hope that helps. Again, please forgive the intrusion.

Paul
BayMicroPaul 12/4/2012 | 9:20:10 PM
re: Bay's ATM Chip Heads Into Battle I can only say that the Bay Solution is extremely competitive from a power, total system cost (note: no exotic RAMS) and real estate perspective. At the risk of sounding glib it really does depend on the application's requirements.


So as to keep this commercial (and vendor) - free as possible. If you have something specific please hit the website with a "request more information". We'll gladly answer any specific questions that you may have.

Paul
mrcasual 12/4/2012 | 9:20:06 PM
re: Bay's ATM Chip Heads Into Battle Hi Mr. Casual,
Those states are not the major items in AAL5 SARing.. The main thing is that for each VCC, you need to buffer the cells until you receive the last AAL5 cells.. It is the cell buffer that required the largest amount of memory..


Yep, I did do AAL5 SAR, the first OC-12 one in the world
to my knowledge, but that's a different story.

When I was talking about data structure requirements I
was NOT counting the actual packet/cell memory. Most
(all ?) implementations I am aware of use some kind of
bulk, i.e. cheap, memory to store the cells. The "context"
type memory tends to be more expensive because it
is generally Read-Modify-Write and truly random access
so you can't easily take advantage of bursts.

Sorry for any confusion.
mrcasual 12/4/2012 | 9:20:05 PM
re: Bay's ATM Chip Heads Into Battle I can only say that the Bay Solution is extremely competitive from a power, total system cost (note: no exotic RAMS) and real estate perspective. At the risk of sounding glib it really does depend on the application's requirements

If you can, please just describe the number and types
of interfaces on the Montego. That would go a long way
to helping.

All people are looking for is something like the following.
Note: I made up the numbers.

The Montego has:

1 - SPI4.2 interface (bi-dir)
1 - PCI 32bit/66MHz
2 - DDR DRAM (36bits/200MHz bits data on each)
2 - ZBT SRAM (18 bits/133MHz)
....
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