SAN FRANCISCO -- The Advanced Switching Interconnect Special Interest Group (ASI SIG) today announced the release of a version 1.1 specification for the Advanced Switching Interconnect (ASI) -- incorporating a variety of new technical features and benefits such as a generic encapsulation mechanism that can be used for any new Protocol Interface's defined (called "PI-2") and the capability to support peer to peer communications between any PCI Express based processors or I/O devices (called "Programmed IO" or "PIO"). The announcement is the first in a series of developments from the ASI SIG in 2005, leading up to the availability of silicon.

ASI technology, based on PCI Express, enables the standardization of proprietary backplane architectures. Common physical-link and data-link layers with the PCI Express standard enable the ASI technology to exploit a vast ecosystem of products currently available in the market. Industry analysts credit the innovative nature of the standard, as well as the ubiquity of PCI Express technology, to the rapid growth and adoption of ASI.

"The strides made over the last year, including the advancements accomplished through the release of the 1.1 specification, further positions ASI as the dominant alternative to fabric-based Ethernet switches," said Pavel Peleska, HA Platform development project leader, Siemens. "We recognize the need for ASI in the industry and continue to see a strong force behind the technology."

The availability of the 1.1 specification signifies the increasing momentum Advanced Switching has gained over the past year in providing a high speed interconnect alternative to Ethernet targeted for backplane and extended backplane usage. Along with its key new features -- including PI2 and PIO translations, the 1.1 release is indicative of the specification maturity and readiness in the industry for silicon availability starting 1H'05.

Protocol Interface 2 (PI2) originally provided a mechanism for Segmentation and Reassembly (SAR) of packets. In the 1.1 specification, the enhancements to PI2 increase its capability as a generic transport for any packet or cell based protocol. This added capability allows silicon vendors to support hardware acceleration of encapsulation for a multitude of protocols.

Programmed IO (PIO) translation provides a standardized method of translating local traffic into ASI packets. By providing a standard method for translating programmed IO traffic, a common software interface can be applied when bridging ASI to a variety of memory mapped protocols such as PCI Express, PCI-X or Hypertransport. The PIO translation is processor independent and enables processor-to-processor, processor-to-IO and IO to IO communication. For PCI Express translation, this added feature to ASI's 1.1 spec will be useful in taking multiple PCI Express-native processors from companies like Intel, PMC-Sierra and Freescale, and clustering them together or providing virtual IO connections to multiple PCI Express endpoints.

"The majority of new protocol interfaces being developed or considered today are envisioned to reuse PI2, so incorporating that capability into ASI's 1.1 spec gives silicon vendors some 'future-proofing' guarantees," said ASI SIG President and Intel's Advanced Switching Initiatives Manager Rajeev Kumar. "The key is to enable vendors to support new PIs that might be created down the road, rather than requiring them to re-spin their product every time a new PI is defined."

Advanced Switching Interconnect SIG (ASI SIG)