Xilinx Chases 100 Gig
By that, Xilinx officials mean they want to offer specialized versions of the chip -- the Virtex-SXT, for instance, packs digital signal processors (DSPs) for applications such as wireless. Building these versions is made easier by the modular columns designed into the chips, something Xilinx first introduced in late 2003. (See Xilinx Reshapes FPGAs.)
The latest version, the Virtex-5 TXT, got introduced yesterday, and it's targeting 100-Gbit/s Ethernet. (See Xilinx Updates Virtex.) Among its goals in life is this simple one: Let people do 100 Gbit/s without needing two FPGAs. Until now, engineers had to dedicate one Virtex-5 to ingress traffic and one to egress traffic, says Anthony Torza, one of Xilinx's technical marketing heads
The TXT takes care of that partly by packing in higher-speed links -- 6.5 Gbit/s serializer/deserializers (SerDes) rather than 3.75 Gbit/s versions.
Those speeds also mean the chip can support the Interlaken standard for chip-to-chip interconnect. That standard, which relies on 6.25-Gbit/s links, got devised by Cisco Systems Inc. (Nasdaq: CSCO) and Cortina Systems Inc. for 40-Gbit/s networking and has been adopted for 100 Gbit/s, too. (See Cortina, Cisco Team Up.)
Getting to the "platform" part, though, Xilinx is providing some pre-programmed circuitry, which the chip industry likes to call "cores," from outside firms. The 100-Gbit/s Ethernet media access controller (MAC) inside the TXT comes from a cores provider called Sarance Technologies Inc. , for instance.
Xilinx is also providing customers with high-speed interfaces from another cores company, Avalon Microelectronics .
Programming software for the chip is available now, but the chips themselves won't sample until later this year. Xilinx expects to be shipping in production in the first quarter of 2009.
— Craig Matsumoto, West Coast Editor, Light Reading