Router Memory Gets a 100G Makeover
The company announced its Bandwidth Engine technology today, a memory design crafted to keep up with a 100-Gbit/s pace while also simplifying systems design.
This could be a big deal. Packets sit in memory while a network processor or Application-Specific Integrated Circuit (ASIC) digs into them. As networking speeds have increased, the time it takes to access data in memory has become crucial.
Not a chipmaker per se, MoSys creates designs intended for use inside an ASIC or Field Programmable Gate Array (FPGA). The company expects FPGAs using Bandwidth Engine to emerge in 2011; ASICs aren't likely to reach volume shipments until 2012.
It's not often that the memory chip business gets a breakthrough, so MoSys -- still a small player, with a market capitalization of $144 million -- is making the most of its moment. The company held a press conference today at DesignCon (a massive geek-out fest for the chip industry) to play up Bandwidth Engine and to emphasize the systems-based approach behind it.
In recent years, issues of memory speed and power have been attacked in isolated fashion, by improving parameters of the chips themselves, CEO Len Perham said at the press conference.
"In an effort to control their costs, the systems guys, without intending to, drive everybody to think that the solution should be some commodity thing that can be sold for a buck," Perham observed. "What we're really doing is thinking about the problem the customer is facing from the point of view of his system, the system architecture."
So, what do you come up with when you redesign memory chips from a systems point of view? MoSys's answer was to turn to a serial interface.
Systems designers use parallel interfaces -- multiple lanes of simultaneous data flow -- to get more data into and out of a chip. But as switch and router interface speeds approach 100 Gbit/s, those parallel interfaces start to involve more lanes, eating up more space and power, not to mention more interfaces on an ASIC.
"You're really pushing the limits of DRAM technology when you're talking 100 Gbit/s," said Bob Wheeler, an analyst with The Linley Group , in a conversation with Light Reading yesterday. "The number of pins and width of these interfaces becomes a challenge."
(Wheeler had no foreknowledge of MoSys's announcement but guessed it would involve a high-speed serial interface. Light Reading will have to call him back to get a Super Bowl prediction.)
Beyond raw speed, MoSys also intends to start taking more actions inside the memory. An arithmetic unit, for instance, will help keep statistics such as packet counts; this will cut down the number of times the system has to access memory, which in turn should speed up data processing.
Bandwidth Engine will be going up against high-end memory chips such as quad data-rate (QDR) SRAMs from Cypress Semiconductor Corp. (NYSE: CY) and Samsung Corp. Another target will be chips based on RLDRAM technology from Rambus Inc. (Nasdaq: RMBS), built by Micron Technology Inc. (Nasdaq: MU) and NEC Corp. (Tokyo: 6701). (Rambus, like MoSys, licenses designs to chipmakers.)
— Craig Matsumoto, West Coast Editor, Light Reading