Opnext Makes Its 100G Move
The Opnext technology was put to the test in an AT&T Inc. (NYSE: T) demonstration being announced today, where a 127-Gbit/s transmission was hooked up between New Orleans and Ellisville, Fla. The 127-Gbit/s figure represents a 100-Gbit/s link with heavy-duty forward error correction (FEC) attached.
Plenty of other 100-Gbit/s trials and even deployments have been announced, including one from Verizon Communications Inc. (NYSE: VZ) yesterday. (See Verizon Expects 100G Deployment in 2010, Verizon Switches On 100G in Europe, Telstra Trials 100G With Nortel, Ciena Sending 100GE Live, and Deutsche Telekom Trials 100G.)
But they've all come from systems vendors. Merchant 100-Gbit/s modules for long-haul aren't ready yet. (They can be had for short-reach distances, as demonstrated by the Finisar Corp. (Nasdaq: FNSR) CFP modules being used in yesterday's Verizon announcement.)
Other trials either haven't used coherent receivers or didn't pack the full 100 Gbit/s into one wavelength, says Ed Cornejo, Opnext's director of product marketing. In some cases, that means the receiving end is looking only at snapshots of the optical signal, because not all the electronics processing is present to verify the signal in real time, he adds.
Opnext is working on a 100-Gbit/s line-side module that will comply with the Optical Internetworking Forum (OIF) framework, which calls for the use of coherent receivers and dual parallel, quadrature phase-shift keying (DP-QPSK) modulation. (Opnext calls it polarization-multiplexed QPSK, or PM-QPSK, but it's the same thing.)
Of course, the module will also be compliant with the Institute of Electrical and Electronics Engineers Inc. (IEEE) 802.3ba standard for 100-Gbit/s Ethernet.
The AT&T test helped Opnext prove out the technologies it wants to stuff into the central ASIC of its 100-Gbit/s module. Opnext isn't giving specifics about timing, but the ASIC design should get to the factory later this year, Cornejo says.
Opnext is building that ASIC on its own, foregoing available merchant pieces such as digital signal processors. Even the high-speed analog/digital converter (ADC), which has to run at 56 billion samples per second, is available from only one company so far: Fujitsu Microelectronics Europe (FME) .
The ASIC design was started by StrataLight three years ago, before its acquisition by Opnext. (See Opnext Steps Up With StrataLight.) StrataLight did that to avoid what happened in the 40-Gbit/s generation, when Sierra Monolithics (SMI) was the only source of serializer/deserializer (SerDes) chips. During a period when Sierra stumbled, module vendors were stuck.
"SMI pretty much held the industry at ransom when they had their problems. We didn't want that to happen again," Cornejo says.
SMI has since been acquired by Semtech Corp. (Nasdaq: SMTC)
Meanwhile, CoreOptics released a challenging 40-Gbit/s SerDes in mid-2008, with promises to do a 100-Gbit/s chip eventually. (See Semtech to Buy Sierra Monolithics , Broadcom Passes on 40-Gig, CoreOptics Intros 40G Serdes, and Sierra Strikes Forth for 100G.)
Opnext's 100-Gbit/s ASIC will be built on silicon, using CMOS processes. But silicon isn't suitable for every high-speed component that's needed in a transceiver module. Opnext is building a multiplexer/demultiplexer chip out of silicon germanium, for instance. (See Opnext Builds 100G Mux/Demux.)
— Craig Matsumoto, West Coast Editor, Light Reading