100G Ethernet

NetLogic Tries Out 100GigE

NetLogic Inc. is announcing what appears to be the industry's first silicon 100-Gbit/s Ethernet physical-layer chip, an expected but crucial step in the development of eventual 100-Gbit/s gear.

The chip, built with ordinary complementary metal-oxide semiconductor (CMOS) processes, would give NetLogic a surprising, albeit temporary, lead over bigger chip names including Applied Micro Circuits Corp. (Nasdaq: AMCC), Broadcom Corp. (Nasdaq: BRCM), and Marvell Technology Group Ltd. (Nasdaq: MRVL).

The 100-Gbit/s PHY, being launched today, comes from one of NetLogic's few acquisitions. About a year ago, the company picked up Aeluros for $57 million in cash, plus another $20 million in possible incentives that might have kicked in by now. (See SerDes Pays Off and A Gap at 100Gig.)

NetLogic makes a combined processor and memory chip that goes on switch/router cards; it's a cousin to network processors. Aeluros worked down at Layer 1, developing 10-Gbit/s physical-layer chips.

Ethernet PHY chips end up getting integrated with media access controllers (MACs), but since neither NetLogic nor Aeluros has deep experience at designing MACs, the company is looking elsewhere. To that end, some kind of partnership with a big-name chip company is set to be revealed soon, says Kelvin Khoo, NetLogic's senior director of business development.

Getting in early
It's arguably early to begin offering these chips, even though the Institute of Electrical and Electronics Engineers Inc. (IEEE) 802.3ba task force for 40- and 100-Gbit/s Ethernet is well underway. AMCC tells Light Reading via email that customers expect 100-Gbit/s systems to be required in field trials in the second half of 2010, with parts likely required three to six months ahead of that.

But NetLogic wants a headstart. When Aeluros worked on its CMOS-based 10-Gbit/s chip, it was already lagging the devices made of silicon germanium (SiGe), says Siddharth Sheth, a NetLogic director of marketing who'd worked at Aeluros.

"We found ourselves on the outside looking in, because there was a sudden rush to build first-generation 10-Gbit/s systems with anything that was available," Sheth says. "Then the market slowed down, and there wasn't a need to build next-generation systems. With 100-Gbit/s, we don't want to make that mistake."

There's also the fact that NetLogic could use the chip itself, having recently announced a 100-Gbit/s-ready processor. (See NetLogic Ships Chips.)

Supporting 40 Gbit/s
The first version of the PHY chip will begin sampling in December, but NetLogic has some immediate tweaks it wants to make.

Support for 40-Gbit/s Ethernet would be one example. The IEEE high-speed group crafted its 40-Gbit/s rules later than those for 100 Gbit/s, possibly a byproduct of 40 Gbit/s coming late to the party. (See 100-GigE, 40-GigE Live in Peace and 40 GigE Could End Standards Spat.)

"We didn't have time to embed that in this version of the chip," Sheth says.

NetLogic would also like to accommodate faster serializer/deserializers (SerDes). The first version of the chip provides 10 lanes of traffic running at 10 Gbit/s each, but systems vendors are expected to want an option for four lanes of 25 Gbit/s, too. Getting those 25-Gbit/s lanes perfected is going to take some more time, though.

The 40-Gbit/s support and the 25-Gbit/s SerDes should be available in the second version of the chip, which should be available in about six months, Khoo says. That chip appears likely to be the version that will go into production volumes when NetLogic is ready, probably late next year.

— Craig Matsumoto, West Coast Editor, Light Reading

atorza 12/5/2012 | 3:27:31 PM
re: NetLogic Tries Out 100GigE This implemenation was conceived with Xilinx and Sarance to offer a low risk cost-reduction of our industry first 100GE MAC implemenation (running traffic today). Using the Netlogic part and our new Virtex-5 TXT FPGA (sampling now), customers can reduce the chipcount required for 100GE from 12 (10 PHYs + 2 FPGAs) to 4 (3 QuadPHYs + 1 FPGA).

Details can be found on our website:
Techonline where I describe the evolution of this implementation:

Anthony Torza
Technical Marketing, Xilinx
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