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100G Ethernet

100G Startup Bags $7.2M

Another 100-Gbit/s startup got funding today -- literally, today.

Israel-based MultiPhy Networks Ltd. just signed the term sheet on a round totaling about $7.2 million, chairman Menachem Abraham tells Light Reading. You might recall Abraham from the early Mintera Corp. days; he was a founder there. (See Mintera Freshens Up Long-Haul.)

The money comes from Vertex Venture Holdings and Maayan Ventures Ltd. -- the two of which had already put about $4 million into MultiPhy -- and a new, unnamed investor.

MultiPhy has been stealthy, with only 15 employees and no Website. But it came clean at OFC/NFOEC with a paper on a 111-Gbit/s receiver using dual polarization, quadrature phase-shift keying (DP-QPSK) modulation.

It's one of a handful of known startups pursuing different aspects of long-haul 100-Gbit/s transmission. (See OFC/NFOEC: Startups Chase 100G.)

The chips necessary for 40- and 100-Gbit/s Coherent detection include an analog-to-digital converter (ADC) and a digital signal processor (DSP). Commercially available ADCs and DSPs lack the horsepower, so the area's become a fertile ground for research. Fujitsu Microelectronics Europe (FME) has produced an ADC that's available commercially, but some companies such as CoreOptics Inc. and Opnext Inc. (Nasdaq: OPXT) have taken to designing the chips themselves.

MultiPhy sprang from the research of Dan Sadot, chair of the electrical and computer engineering department at Ben-Gurion University of the Negev. Its chips invoke a combination of anti-alias filtering and maximum likelihood sequence estimation (MLSE).

MLSE is a familiar method for cleaning up electrical signals, and companies such as ClariPhy Communications Inc. , CoreOptics, and Menara Networks have used it at 10 Gbit/s. (See ClariPhy Cleans Up 10-Gig, CoreOptics Pushes MLSE, and Menara Demos IP Video Solution.) But the technique hasn't gotten as much mention at 40 and 100 Gbit/s.

MultiPhy's trick is to run the ADC at 28 billion samples per second, half the norm for a 100-Gbit/s receiver. It does that by using an anti-aliasing filter to halve the bandwidth of the 100-Gbit/s signal, which allows for a slower ADC. Afterward, as MultiPhy restores the speed, MLSE cleans up the signal.

MultiPhy has done 100-Gbit/s coherent experiments with its technology, but the company will target another market first: direct-detection receivers, i.e., those that aren't coherent (incoherent?). The result would be an intermediate step, a receiver that can accept 40-Gbit/s and 100-Gbit/s signals on fiber intended for 10 Gbit/s but doesn't eat up as much power as a coherent receiver would.

That could be particularly useful for metro and regional spans, compared with the power consumption and the cost of coherent receivers. "Looking five to 10 years out, we have a hard time imagining that everything will be done with coherent transponders," Abraham says. "In metro and regional networks, there are quite a few benefits to not going to coherent."

MultiPhy hasn't gotten to the expensive part of its development, namely, building the chips. That's where much of the $7.2 million will be going. The company expects to complete its chip design within a few months, and sample chips could follow in the third quarter, Abraham says.

— Craig Matsumoto, West Coast Editor, Light Reading

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