Comms chips

Cavium Targets Intel With Multicore SoC Line

Cavium is introducing a line of multicore system-on-a-chip (SoC) products that will be based on ARM Ltd. technology, rather than on the MIPS Technologies architecture, in order to target a much wider range of applications including control plane and data plane applications.

With the introduction of the Octeon TX line, Cavium Inc. (Nasdaq: CAVM) intends to attack Intel Corp. (Nasdaq: INTC) more or less across the board, including where Intel has thus far been virtually unassailable: in the data center.

The new Octeon line, the TX line, is composed of four product families, each optimized for a different set of applications. The two product families at the entry level -- the CN80XX and CN81XX, each with 1-4 cores -- will begin sampling shortly; these are aimed at control plane applications, virtualized gateways and other applications. The 8- to 24-core CN82XX and CN83XX are scheduled to begin sampling in Q3.

The company is in production with its 48-core devices for NFV applications, Venkat Sundaresan, director of the company's Infrastructure Processor Group, told Light Reading. Cavium expects to be able to scale up to single SoCs with up to 96 cores.

"We can add a lot more physical cores than Intel or any other company can, at a lower power and price," Sundaresan said.

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Also key is being able to use the same or compatible software across all Cavium's products, across the range of price points, which Sundaresan argued will make it easy to migrate the technology all the way from the edge up to the core.

The product line, the company said, is optimized to run multiple concurrent data and control planes for security and router appliances, NFV and SDN infrastructure, service provider CPE, wireless transport, NAS, storage controllers, IoT gateways, printer and industrial applications.

Previous products based on the Octeon SoC architecture are already being used in applications for data plane as well as control plane with embedded software. Control plane applications requiring wider software ecosystem and support traditionally have been addressed by the x86 architecture, Cavium noted. The open, service-centric networks need lower-cost alternatives for control plane, and superior ecosystem and networking performance for data plane. Those considerations led Cavium to the ARM architecture rather than MIPS.

— Brian Santo, Senior Editor, Components, T&M, Light Reading

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