Xilinx Intros 100G Gearbox
The global demand fueled by the surge in multimedia content and the rise of cloud computing is creating an unquenchable thirst for more bandwidth. This in turn is driving the need for adoption of more high-speed 100G interfaces with higher port densities in the optical and packet networking equipment across the network – core, aggregation, data center and transmission. The move toward increased numbers of 100G interfaces per line card in the core and aggregation nodes has become critical to achieve scale, network simplicity and an overall cost reduction in running and managing networks. CFP2 optical modules that are half the size of CFP modules with significantly lower power consumption require an external 100G gearbox to achieve density gains and power advantages based on their form factor. Further gains are achieved when both the CFP2 modules and the gearbox conform to 100GE, OTU4 and 10x 10 MSA specifications, which require using 4x 25G and 10x 10G serial links schemes for systems side interfaces. A single IP core for connecting multiple 100G interfaces into a single chip takes integration to the next level. Combining the Xilinx Dual 100G Gearbox with other OTN or packet processing functionality in a single chip provides an unprecedented level of integration, while reducing overall systems power and lowering the total BOM costs by up to forty percent.
“The anticipated pace of growth in the 100G market provides an unprecedented opportunity in the optical transmission space for FPGA vendors to secure a domineering role in providing chips for a far-reaching period of time,” said Mark Lutkowitz, Principal of Telecom Pragmatics. "Xilinx’s Gearbox IP will be a key enabler in meeting the higher density and lower power demands for second-generation CFPs.”
Xilinx Inc. (Nasdaq: XLNX)