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Comms chips

Siverge Picks Up Chip Trail

Startup Siverge Networks wants to revisit the glory days of PMC-Sierra Inc. (Nasdaq: PMCS) and similar chip companies, claiming it can pick up where they left off.

The company is bringing out a line of chips for handling Layer 1 and 2 transport -- a market that led companies like PMC-Sierra, Applied Micro Circuits Corp. (Nasdaq: AMCC), and Vitesse Semiconductor Corp. (Nasdaq: VTSS) to riches during the dotcom bubble. (See PMC-Sierra Struts on the Street and Semiconductor Merger Mania.)

Those companies cooled substantially during the telecom downturn and started looking into other markets -- storage, in particular. (See AMCC Moves Into Storage, PMC Bites a Bit of Agilent, and Vitesse Unloads Storage Biz.)

And, of course, they've had some other troubles. (See Vitesse Execs Get the Axe.)

This adds up to a gap in what should have been the development of physical-layer chips, Siverge CEO and chairman Yuval Berger claims. Over time, chips tend to get integrated together and to pack on more functions -- but the big TDM-chip leaders of 1999 haven't been able to make those investments.

"There's been no innovation in the field for a decade," Berger says, maybe with a touch of hyperbole.

Looking at just the past few years, though, Berger says there have been the usual advances in manufacturing -- such as chips getting smaller -- but without any accompanying big-picture integration developments.

That, he claims, has left equipment vendors hungry for new types of chips. "When they're forced to be as efficient as possible and to integrate more functions onto a linecard, today they are going back more and more to FPGAs."

The reason those chips are still important is that, even though Ethernet and IP are taking over the telecom world, Sonet (Synchronous Optical NETwork) and SDH (Synchronous Digital Hierarchy) and other TDM interfaces aren't going away for years.

So, here's the integration play Siverge proposes -- one chip to handle, among other protocols: Frame Relay; Asynchronous Transfer Mode (ATM) including inverse multiplexing; Sonet/SDH with add-ons such as virtual concatenation (VCAS); and the Plesiochronous Digital Hierarchy (PDH) protocols (T1/E1 stuff).

The SV3640 family of chips handle all those protocols at varying line speeds up to OC48 (2.5 Gbit/s). Siverge is also introducing cheaper versions that focus on subsets of the protocols, such as the SV3620 chips that include Ethernet-over-Sonet coverage. Those would be the chips Siverge was willing to drop hints about in October, before it was revealing its full business plan. (See Siverge Networks and Spotlight Ethernet.)

The SV3640 and its spinoffs are collectively called the Griffin family and are expected to sample in January.

Ethernet chips would come next, with samples possible in early 2010. Mixing the two -- Ethernet and all manners of TDM -- would be a logical step, but Berger concedes this isn't feasible just yet.

— Craig Matsumoto, West Coast Editor, Light Reading

Munster 12/5/2012 | 3:24:59 PM
re: Siverge Picks Up Chip Trail Picking up where PMC, Vitesse and AMCC have left off? Am I missing something? All of these companies are desperately seeking a source of any profit and Siverge claims that with 12 MUSD investment that they've cracked the code that these guys couldn't? Where is your critical analysis, Craig?!
And while integration sounds great on paper, it rarely works out being the "killer app" that companies expect. And for the record, remember PMC's ADM-on-a-chip? How big a success was that? Any highly integrated ASSP product is going to be risky as there is no way to fix the bugs without a re-spin. The more complex the chip, the more likely the re-spin.
And finally, "resorting" to FGPAs is hardly a defensive strategy anymore. FPGAs are becoming a truly formidable platform that begs the question why one needs to make an ASSP for these high-end applications. Most Tier 1 vendors use them for highly complex chip solutions - even those who traditionally make their own ASIC chips. And there is good reason - you can fix bugs quickly and the volume in this market simply cannot justify ASSPs as PMC, Vitesse and AMCC have worked out.
So when is the shoe going to drop for Siverge?
Pete Baldwin 12/5/2012 | 3:24:57 PM
re: Siverge Picks Up Chip Trail You're not missing anything, Munster, except maybe the word "claiming" in the story lead. I'm not saying Siverge is a guaranteed success; just saying they're out there.

I do believe it's possible for them to have leapfrogged PMC et.al., because those companies have been putting their R&D $$ elsewhere -- plus, chip development isn't as expensive a proposition as it used to be.

Regarding FPGA vs. ASSPs, that's an argument that can go back and forth infinitely. Everything you say about FPGAs sounds true, and their role in the industry has definitely changed/expanded. Then again, don't FPGAs still take up more space than an ASSP? If someone's willing to develop that ASSP, I'd think most vendors would embrace the chance to replace their FPGAs. (In concept, at least; we all know that startups can have a hard time getting sales into big-company customers.)
OSXman 12/5/2012 | 3:24:56 PM
re: Siverge Picks Up Chip Trail Can someone please tell me what is technically new and different here?
linbin 12/5/2012 | 3:24:56 PM
re: Siverge Picks Up Chip Trail This start-up will run out of money before they get a working chip out. Many cases happen in the past for such star-up respinning a super chip again and again.
Munster 12/5/2012 | 3:24:54 PM
re: Siverge Picks Up Chip Trail Hi Craig

Fair enough. You are claiming. Still doesn't answer my questions though. Here's another one: why have the others stopped investing in this area? Answer: you can't make money here!

The FPGA vs ASSP discussion is interesting, as I believe it is only now that we can start taking FPGA's seriously. Up to now, the key issue was not space, but power consumption. But, with the move to 65nm and 40/45nm geometries this is no longer an issue.

And, I don't see chip development getting cheaper - unless you stay on a much larger geometry, which will lead to higher power consumption with more integration. If you want to follow the FPGAs into 65nm and 40/45nm to meet the same performance targets, then it's a much more daunting economic proposition (we're talking 40 or 50m USD).

Again, can't see this happening...
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