Avago Technologies leads industry with 17-Gbit/s SerDes performance in 65 nm CMOS process

September 13, 2007

1 Min Read

BOBLINGEN, Germany -- Avago Technologies today announced it hasproven 17 Gbps SerDes performance in 65nm CMOS technology. Continuing itslegacy of embedded SerDes leadership, Avago's current generation representsa reduction in power and area of up to 25 percent. With close to 45 millionSerDes channels shipped, Avago has established a solid track record ofdelivering reliable, high-performance IP and now continues to push ASICdesign limits by validating 17 Gbps SerDes in 65 nm.

The modular architecture and multi-rate capability of Avago's SerDes core ishighly scalable, and flexible power management options give systemmanufacturers the option to reduce power by up to 40%. Ideal for Ethernetswitches/routers and storage switch applications, the embedded SerDestechnology will support a broad range of standards, such as PCI-Express,Fibre Channel (1GFC - 16GFC), CX-4, XAUI/ CEI-6G, XFI and 802.3ap and issuitable for both chip-to-chip and backplane applications. Avago's ASICtechnology also provides an on-chip BERT for channel bit-error optimizationand an on-chip high speed scope allowing system designers to view, in thetime domain, the received signal internal to the chip.

"Avago's history of being early to market with high performance SerDes IPcontinues with our demonstration of a 17 Gbps core," said James Stewart,vice president of Avago Technologies' ASIC products division. "With provenperformance in 65nm silicon, we are positioned to meet the demands of ourleading edge enterprise customers for ever-increasing density and speed."Avago Technologies incorporates testing capabilities as early as thedefinition of system-level architecture and accounts for in-circuitmanufacturing test, functional test, system turn-on and debug, and fielddiagnostics. The result is faster time to market of reliable high-bandwidthnetworking and storage systems.

Avago Technologies Pte.

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