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SyntheSys Supports Stressed Eye

SyntheSys Research will present a new integrated, stressed eye generator option for its BERTScope analyzer family

March 7, 2005

1 Min Read

MENLO PARK, Calif. -- SyntheSys Research will present a new integrated stressed eye generator option for its BERTScope™ analyzer family at OFC in the Anaheim Convention Center, March 8 through March 10, 2005. You are invited to visit the BERTScope Booth #1030 between 10:00 p.m. and 4:00 p.m. (5:00 p.m. on March 8 and 9) for a demonstration.

SyntheSys Research BERTScopes combine eye diagram analysis, jitter analysis, and BERT (bit error ratio test) pattern generation and error analysis in a single instrument. The new integrated stressed eye option allows the BERTScopeTM to overlay controlled levels of jitter and an adjustable sinusoidal interference signal on top of data patterns for compliance testing of receivers.

High-speed interfaces such as 4 Gb/s Fibre Channel, second and third generation Serial-ATA, Serial Attached SCSI, Fully Buffered DIMM, SONET, SDH, 10 Gb Ethernet, and 11 Gb/s OIF-CEI require verification of compliance with input jitter tolerance levels. While previously requiring racks of expensive and difficult to calibrate equipment, stressed eye tests can now be flexibly controlled and generated with the BERTScope option. Integrated generation of sinusoidal, random, and bounded, uncorrelated jitter offers a calibrated output addressing automated measurements to multiple standards.

BERTScope’s stressed eye is created by adding programmable sinusoidal, deterministic, random and bounded jitter to the data pattern generator. In addition, external inputs for user generated stress are provided for extra versatility.

SyntheSys Research Inc.

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