Lucent Boosts FPGA Performance

Lucent developed FPGA technology that more than triples operating speed and gate density over previous generation devices

July 3, 2000

5 Min Read

ALLENTOWN, PA--Lucent Technologies (NYSE: LU) Microelectronics Group, the world leader in communications semiconductors, today announced a field-programmable gate array (FPGA) integrated circuit (IC) technology that more than triples operating speed and gate density over previous generation devices.

This boost equips Lucent's ORCA(r) FPGAs to handle the most demanding wireless, broadband access, asynchronous transfer mode (ATM) and synchronous optical network/synchronous digital hierarchy (SONET/SDH) cores from Lucent's intellectual property library.

The new FPGA technology also gives design engineers the ability to embed field-programmable logic blocks into communications systems-on-a-chip (SoC) that are deployed as application-specific integrated circuits (ASICs) or application- specific standard products (ASSPs). This gives designers the ability to incorporate last-minute changes in networking standards or customer specifications into complex IC designs, allowing higher levels of system integration while meeting accelerated system development schedules.

The new technology, called ORCA Series 4, is based on Lucent's COM2 modular SoC fabrication technology (0.13-micron physical gate length). Lucent will deploy the technology in a variety of silicon offerings: generic FPGA devices, embedded programmable blocks in SoCs, and in the company's field-programmable system chips (FPSCs) - FPGA devices integrated with a standard-cell core of widely used communications intellectual property (IP). Both the embedded block and FPSC approaches give designers the flexibility to implement established functions in standard-cell logic and target functions that may change into programmable blocks.

The first ICs using ORCA Series 4 technology are slated for introduction in the third quarter of 2000. They are the OR4E6, a 600K-gate networking FPGA designed to hold IP such as Lucent's 32-channel, 32-group inverse multiplexing for ATM (IMA) core; and the ORT8850H/L devices, a pair of FPSCs with Lucent's 850 megabit-per-second clock/data recovery core and either 600K or 200K programmable system gates for customer IP. These devices are designed for high-speed system backplane applications and SONET/SDH interfaces.

"ORCA Series 4 technology extends the spread of silicon offerings on which we deliver the industry's broadest line of communications-specific IP," said Samir Samhouri, general manager of Intellectual Property Solutions in the Networks and Communications unit of Lucent's Microelectronics Group. "The technology supports second-generation FPGA integration capability by embedding field-programmable blocks in ASICs and ASSPs, and it enhances the first-generation hybrid standard-cell/FPGA approach we pioneered with ORCA Series 3 FPSCs. It also gives our generic FPGAs the ability to support even more demanding IP. As a result, systems manufacturers can preserve circuit designs using the same IP cores across product life cycles - in prototypes for faster development, early production runs for quick marketplace introduction, and economical volume production."

Characteristics that make ORCA Series 4 technology "networking ready" include support for more than 1.5 million usable system gates on a single chip and internal performance of more than 200 megahertz (MHz) and input/output (I/O) performance of more than 416 MHz. It operates at 1.5 volts with support for multiple I/O interface standards at 3.3, 2.5 and 1.8 volts. The architecture is peripheral component interconnect (PCI) local bus compliant and has built-in 8-bit, 16-bit and 32-bit interfaces to the PowerPC(a) 860 and PowerPC II microprocessors. It uses a new embedded AMBA(b) specification 2.0 AHB multi-master system bus to handle communication at rates up to 200 MHz between the microprocessor interface, configuration logic, all embedded-block RAMs, FPGA logic and embedded standard-cell blocks. The architecture also features up to eight dual-source PLLs for generating up to sixteen conditioned clock signals, including new phase-locked loops (PLLs) that provide standards-compliant clock conditioning for DS-1/E-1 and STS-3/STM-1 applications and generic PLLs that run at speeds up to 416 MHz.

Key architectural enhancements include 512x18 embedded-block RAMs that support Quad-port RAM, FIFOs, multiplier and CAM applications directly without the use of any other logic. I/O support includes HSTL, SSTL, GTL, GTL+, LVDS, LVPECL, PECL signaling standards and direct support for double data rate (DDR) and ZBT memory interfaces. Also supported at each I/O is the ability to support directly in hardware 2x/4x uplink/downlink speed capability (416 MHz external to 104 MHz internal, for example).

Logic block speed enhancements result from advanced 0.13-micron processing as well as architectural improvements to the ORCA architecture that combines LUT logic, distributed RAM capability and PAL-like logic in the same programmable logic block. Major improvements to general routing allow up to 3x speed improvement over previous architectures while new clock routing structures for global and local clocking have been tuned to significantly increase speed. It meets universal test and operations physical layer interface for ATM (UTOPIA) Levels 1, 2 and 3, and proposed specifications for Level 4 (10 gigabit-per- second (Gbit/s) interfaces).

The new ORT8850H/L FPSCs build on the hybrid approach first introduced by Lucent in 1998. The FPSC family currently includes the OR3TP12 and OR3LP26B devices for 64-bit-wide, 66 MHz PCI interfaces, and the ORT4622, a full-duplex 2.5 Gbit/s system backplane transceiver for high-speed data transfer. The ORT8850H/L devices both embed an eight-channel 850 Mbit/s CDR macro together with 600K FPGA gates (ORT8850H) or 200K FPGA gates (ORT8850L), thus allowing bandwidth up to 6.8 Gbit/s (full-duplex) over serial links. Additional features for the ORT8850H/L devices include optional 8B/10B encoding/decoding or SONET scrambling, channel alignment capabilities, SONET transport overhead insertion/extraction, and full I/O redundancy for all eight channels.

Also supported on the device is up to three eight-bit, full-duplex RapidIO(c) buses, each sending DDR data at up to 311 MHz (622 Mbit/s) for a total bandwidth of 15 Gbit/s. The RapidIO interface includes a dedicated 4x PLL used to center the transmit clock in the data eye and both the CDR interfaces and the RapidIO interfaces use fully on-chip terminated LVDS inputs and outputs to allow for backplane driving or chip-to-chip applications. Lucent also provides intellectual property VHDL cores for packet delineation, TOH insertion/extraction, pre-defined backplane interfaces for its Atlanta ATM/IP switching chip set, and payload termination for its TADM04622 SONET/SDH framer.

The ORCA Series 4 technology, including the OR4E6 and ORT8850H/L devices, will be supported by the ORCA Foundry Development System 2000 design software, now available in alpha version, with production scheduled for September. Both the OR4E6 and the ORT8850H are slated for availability in the third quarter of this year, with unit pricing in quantities of 10,000 set at $300.00 for the OR4E6 and $350.00 for the ORT8850H. The ORT8850L is slated for availability in the fourth quarter of this year with unit pricing in quantities of 10,000 set at $75.00.

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