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PMC-Sierra enables cost-effective carrier-class Sonet/SDH metro transport network upgrades with OC-48/STM-16 and OC-192/STM-64 chipset
June 3, 2002
SANTA CLARA, Calif. -- PMC-Sierra (NASDAQ:PMCS) today announced the CHESS-III(TM) chip set for aggregating, grooming, and transporting 2.5Gbps and 10Gbps metro services. The chip set establishes a new benchmark for technology and innovation. CHESS-III simplifies design and network management and substantially reduces carrier systems costs. The chip set enables original equipment manufacturers (OEMs) to leverage deployed line cards into new and more advanced systems, thereby preserving existing service provider investment and infrastructure. The CHESS-III chip set includes the PM5376 TSE-Nx160(TM) STS-1/AU-3 cross-connect device, PM5326 ARROW-2x192(TM), and PM5324 ARROW-1x192(TM) SONET/SDH framers. CHESS-III is ideal for Multiservice Provisioning Platforms (MSPP) (see Figure 1), sub-wavelength cross-connects, and Add/Drop Multiplexers (ADMs) for metropolitan transport markets. The CHESS-III chip set can be used to seamlessly upgrade currently deployed CHESS-I(TM) and CHESS-II(TM) systems, or can be deployed in new, scalable metro architectures. The TSE-Nx160 device grooms sub-wavelength traffic and features the industry's first non-blocking, scalable STS-1/AU-3 cross-connect. This unique chip architecture enables metropolitan transport equipment to scale from 160 to 640 Gigabits. The ARROW-2x192 and ARROW-1x192 are the industry's highest density OC-48/STM-16 and OC-192/STM-64 transport optimized devices integrating the latest SONET/SDH transport features for both current and next-generation metropolitan networks. All devices in the CHESS-III family interoperate through the use of PMC-Sierra's industry leading, standard 2.5Gbps backplane I/O technology to simplify system design and increase time-to-market for service provider OEMs. "PMC-Sierra worked together with the leading world-wide service provider equipment vendors to build a state-of-the-art architecture. Our CHESS-III chip set architecture incorporates the newest transport framer features and solves the issues of STS-1 and AU-3 cross-connect scalability and non-blocking which are major stumbling blocks in today's metro equipment networks," said Steve Perna, vice president and general manager of PMC-Sierra's Optical Networking Division. "The CHESS-III chip set reduces carrier operating expenses by enabling the deployment of a single hardware platform that can be re-used in multiple areas of the network." PMC-Sierra Inc.
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