PMC Intros MIPS Processors

Expands lineup with three new 64-bit MIPS-based processors and multiple I/O interfaces for networking, storage, and security apps

June 17, 2003

5 Min Read

SANTA CLARA, Calif. -- Today at the Embedded Processor Forum, PMC-Sierra(TM), Inc. (Nasdaq: PMCS - News) announced two RM9000x2GL highly integrated 1 GHz 64-bit MIPS-based(TM) multiprocessors, the RM9220 and RM9224. The RM9000x2GL multiprocessors offer customers additional I/O interface options such as 3 ports of 10/100/1000 Ethernet MAC, Generic Packet Interfaces (GPI), and PCI or HyperTransport(TM). As a result, the RM9000x2GL multiprocessors can be used in a wider range of applications such as enterprise routers and switches, network protocol processing and conversion servers, storage systems, DSLAMs and Web servers. The dual-core devices can also be used as a high-performance and compact solution for VPN/ Firewall and other security applications in conjunction with appropriate encryption engines.

"The RM9000x2GL builds upon our successful RM9000x2 MIPS-based dual CPU core architecture. The addition of multiple I/O interfaces provides us with the ability to meet design requirements in a broader customer base. Our RM9000x2 multiprocessor was originally designed for control and data plane networking applications and the RM9000x1 for storage and wireless markets. Now with the RM9000x2GL we are pleased to be able to design our RM9000 family of products into over a dozen types of applications," said Tom Riordan, vice president and general manager of PMC-Sierra's Microprocessor Products Division. "PMC-Sierra offers the industry's most scalable, stand-alone MIPS-based processors and we are committed to extending our RM5200, RM7000 and RM9000 families with higher integration and performance while maintaining low power."

The RM9000x2GL integrates high-speed memory and I/O interfaces to create low latency accesses into the main memory and high bandwidth to the I/O devices. The I/O interfaces include three Ethernet MACs, PCI or HyperTransport, DDR SDRAM controller, SysAD and a local boot bus:

  • The three Ethernet MAC interfaces each operate in 10/100/1000 Mbit/s and support industry standard MII (10/100 Mbit/s), GMII (1000 Mbit/s), and TBI (1000 Mbit/s) interfaces to standard Ethernet transceivers. Combinations of these Ethernet MAC interfaces can be bypassed to provide 8-bit, 16-bit, or 32-bit GPI interfaces.

  • The POS-PHY(TM) Level 3 (PL3) and FIFO-like interfaces offer high bandwidth and easy to use interfaces running up to 200 MHz for connecting external packet processing FPGAs and ASICs.

  • An integrated 32-bit PCI controller provides PCI 2.1 compliant operation at both 33 MHz and 66 MHz.

  • An 8-bit HyperTransport interface can operate up to 500 MHz DDR.

  • A 200 MHz integrated DDR SDRAM interface provides 25.6 Gbit/s of memory bandwidth.

  • The local boot bus provides connectivity to lower speed devices such as boot ROM and Flash.



In a separate release:

Today at the Embedded Processor Forum, PMC-Sierra(TM), Inc. (Nasdaq: PMCS - News) introduced the RM7900, RM7965 and RM7935 MIPS-based(TM) processors for networked laser printers, storage systems, personal video recorders, high-definition televisions, set-top boxes, routers and switches (see table 1). The RM7900 processors integrate PMC-Sierra's proven high-end RM9000 family CPU core, the E9000, to bring optimized performance efficiencies realized in networking to printer and advanced consumer applications. Seamless, low cost scalability is achieved by utilizing the industry compatible and enhanced 64-bit or 32-bit SysAD bus which interfaces to a variety of memory, system controllers and ASICs. The RM7900 products represent the industry's first stand-alone MIPS(TM) architecture processors with speeds in excess of 600 MHz and on-chip hardware and software debugging instruction modules, ECC and EJTAG to offer improved data reliability.

"PMC-Sierra's RM7900 MIPS-based processors allow our printer, advanced consumer and networking customers to scale up while extending the life of their current systems and reducing costly redesigns," said Tom Riordan, vice president and general manager of PMC-Sierra's Microprocessor Products Division. "Our MIPS-based processors offer strong performance characteristics, a large variety of core configurations, competitive pricing, and robust development tool chain."

The RM7900 processor family is designed with the identical E9000 CPU core used in the RM9000 highly integrated multiprocessor family. The efficient, 7-stage, dual-issue pipeline CPU extends performance from 600 to 900 MHz. The E9000 core includes a dual-integer superscalar processor with a two-level cache hierarchy, MMU and sophisticated branch predictor. The branch predictor in the RM7900 family increases the accuracy of prediction to greater than 95 percent. The E9000 core contains 16 KB of instruction, 16 KB of data cache and 256 KB of Level 2 cache.

The RM7900 family processors provide an enhanced high performance legacy MIPS architecture system interface called the System Address/Data Bus (SysAD). These processors support legacy designs with a seamless upgrade path for all RM7000 family and RM5200 family processors while maintaining compatibility with all existing and future companion chips and ASICs that utilize SysAD functionality as well as software. Both the 32-bit and 64-bit SysAD busses are flexible to allow easy interfacing to memory, system controllers or ASICs of varying frequencies. Therefore, either a low cost interface or a faster, high-performance interface can be designed to communicate with any RM7900 family processor allowing customers to extend the life span of their ASICs. This feature also provides seamless future support for subsequent generations of the RM7900 family processors with increased clock speeds.

The RM7900 family processors provide on-chip EJTAG debug modules to ensure smooth and easy debugging for both hardware and software by allowing single-step and state examination. The inclusion of a pipeline-rate branch instruction trace buffer facilitates debugging under operating conditions. As data rates increase and new designs become more complex, most customers require ECC support for next-generation designs. The RM7900 family of processors incorporates ECC on the Level 2 cache to provide increased data integrity by checking for errors and, when necessary, correcting the data as it is being transmitted or read.

PMC-Sierra Inc.

Subscribe and receive the latest news from the industry.
Join 62,000+ members. Yes it's completely free.

You May Also Like