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Programmable, single-chip architecture designed for high-bandwidth streaming data processing and scaleability to 40 Gbit/s
June 15, 2001
FREMONT, Calif. -- Cognigine Corporation, an emerging leader in broadband and optical networking semiconductors, today introduced a new fully programmable, single-chip network processor architecture designed to provide next-generation networks with optimized high-bandwidth streaming data processing and scalability to 40 Gigabits per second and beyond. The architecture was introduced today at the Embedded Processor Forum in San Jose, CA, by Rupan Roy, Founder, Chairman and Chief Technical Officer of Cognigine. Initial products based on the new architecture will deliver full duplex, 10 Gbps wire-speed performance, and integrate all fast-path processing functions between the framer and the fabric interface. The advanced multi-processor architecture incorporates a wide range of proprietary features including a multi-issue communications-specific processor core, high-speed on-chip switch fabric interconnect, and innovative variable instruction set capability. "The high wire-speed performance and full programmability of the Cognigine architecture will make it the network processor of choice for next-generation communications applications, such as routers in the Metro Access and Metro Core where the greatest changes in traffic and services are occurring," said Nick Kucharewski, Cognigine's President and CEO. "The Cognigine single-chip architecture also provides other significant advantages over higher-cost multi-chip network processor solutions, including board space and power consumption, which translates into greater port density." Cognigine Corp.
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