AMCC introduces its 10-Gbit/s dual clock data recovery device for XFP module market

February 28, 2005

2 Min Read

SAN DIEGO -- Applied Micro Circuits Corporation (AMCC) (NASDAQ:AMCC) today announced the S19233, a 10Gbps dual Clock Data Recovery (CDR) device with Electronic Dispersion Compensation (EDC) and the S4850, a dual OC-48 CDR. The first in a series of 10Gbps dual CDRs with EDC, AMCC's S19233 is designed for use primarily in XFP MSA modules. The dual CDR mitigates fiber properties, such as Chromatic Dispersion and FR-4 traces up to 30", and boasts industry-leading jitter tolerance (0.8UI) and jitter generation (35mUI) specifications. The combination of these capabilities enables greater design flexibility and creates a cost-efficient opportunity for customers to leverage their existing systems for a variety of applications.

The S19233 supports 10 GbE/FC/SONET/SDH/FEC transmission standards at market-leading data rates from 9.9 to 11.3Gbps. Featuring a small footprint of 6x6 mm(2), the device contains dual CDRs that provide fully integrated clock recovery signal conditioning capabilities for low-power, 10Gbps applications. The S19233 is an integral part of a flexible system solution and can be connected to AMCC's S19237 ser/des device.

"We think the performance of the S19233 as a dual CDR will allow for a greater adoption of the XFP MSA module in the marketplace," said Neal Neslusan, director of marketing for AMCC's transport products. "The newest member of AMCC's proven, CDR/EDC portfolio demonstrates our commitment to the 10Gbps market and expertise in delivering greater functionality in the low-power, high-speed devices our customers require today."

The S19233 can be used in the optical interface of SONET/SDH/FEC/10GbE/10GFC equipment, which consists primarily of the serial transmit interface and the serial receive interface. The S19233's system circuitry consists of a high-speed phase detector, clock dividers and equalization circuitry. The device utilizes on-chip clock recovery/clock clean-up PLL components that allow for the use of a slower external clock reference, 155.52 MHz (or equivalent FEC/10GbE/10Gbps FC rates), in support of existing system clocking schemes.

Similar to the S19233, the S4580 CDR derives high-speed timing signals for SONET/SDH-based equipment but for OC-48 plus FEC data rates. The S4850 receives an OC-48 scrambled NRZ signal and recovers the clock from the data. The device outputs a differential bit clock and retimed data. Packaged in a 121-PBGA, the S4850 offers designers a small package outline with low power dissipation (200 mW/channel).

Demonstration at OFC/NFOEC

AMCC will be demonstrating the capabilities of the S19233 CDR in a FEC environment at the Optical Fiber Communication (OFC) Conference and the National Fiber Optic Engineers Conference (NFOEC) in Anaheim, Calif., March 6-11, 2005. For more information about this product demonstration, please visit AMCC in booth #2641 at OFC/NFOEC, which is being held at the Anaheim Convention Center. Exhibits will be open Tuesday, March 8, through Thursday, March 10.

Applied Micro Circuits Corp. (AMCC)

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