PALO ALTO, Calif. -- Denali Software, Inc., the leading provider of semiconductor intellectual property (SIP) and engineering design automation (EDA) tools for memory system design and verification, today announced that its Databahn(TM) memory controller cores are used in Azanda Network Devices Scimitar(TM) AZ61100 OC-48 Traffic Manager/ATM SAR. Azanda configured the on-chip Databahn memory controllers to provide 400 MHz data transfers from DDR-SDRAM memory devices operating at 200 MHz. Azanda's Scimitar chip performs traffic management and ATM segmentation and re-assembly (SAR) functions at full-duplex OC-48 speeds, delivering a total aggregate bandwidth of 5 gigabits per second (Gbps)."We have had great success with Denali's Databahn memory controller in our networking SAR & Traffic Manager products," said Kaushik Patel, vice president of engineering at Azanda Network Devices. "The quality of customer support and turnaround time on technical issues was outstanding. We configured the Databahn core for a 64-bit interface to DDR-SDRAM running at 200 MHz, and it was fully functional at speed in first silicon. Based on our success with the Databahn in our Scimitar(TM) chips, we have chosen to use Denali memory controllers in our next generation Saber(TM) product family of Traffic Managers and ATM SARs.""Databahn is the most comprehensive IP solution available for high-speed memory system design," said Kevin Silver, vice president of marketing for Denali. "We're providing silicon-proven memory controller cores that are fully configurable to meet a broad range of performance and interface requirements, and we support our customers with everything necessary for successful implementation--from pre-hardened memory PHY cores, to specialized I/O pads. Azanda's success with Databahn in its Scimitar product is yet another example of how our IP infrastructure can deliver memory systems for even the highest-bandwidth applications."Denali Software Inc.Azanda Network Devices