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The Programmable Switch Era Is Here... At Last!

Simon Stanley
Heavy Lifting Analyst Notes
Simon Stanley
9/7/2018
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Twenty years after the first network processors were launched, we are now moving toward the fully programmable data plane, with network operator virtualization efforts driving that trend.

Most physical networking systems are being replaced by virtual network functions (VNFs) running on servers at the core and edge of the network. These servers have general-purpose processors or integrated multicore processors with hardware acceleration for security and packet processing. The next stage is replacing the fixed function hardware switches with fully programmable switches based on the latest switch chips. The demand for programmable switches and multicore processors that support high-throughput packet processing is coming from carriers and service providers, and both equipment developers and silicon suppliers are responding to these requests.

This is one of the many key findings in the Heavy Reading report, Multicore Processor and Switch Survey 2018, which is based on an exclusive worldwide survey that drew responses from almost 70 professionals representing 40 different telecom and networking equipment suppliers.

The report charts the use of general-purpose processors, integrated multicore processors and switch chips in networking systems. It includes information about which processors are being used and the performance required in the future, the importance of different features, the use of FPGAs and ASICs, processor vendor rankings and valuable trend data using results from previous surveys.

It also includes information about which switch chips are being used, the switch capacity required, the importance of different features and switch chip vendor rankings.

The first network processors were programmed in machine code and slowly transitioned to C and C++. Most switch chips have some level of programmability, but the development tools for many are restricted to the chip vendors and a few key customers. ASICs and FPGAs are usually designed and programmed using VHDL/Verilog. The development of P4 and other high-level languages for packet processing creates a new opportunity for a fully programmable data plane that is largely independent of the hardware implementation: The results of the survey suggest that companies are starting to take advantage of this.

Integrated multicore processors are available from multiple companies using different core architectures. Intel's x86-based Xeon D processors are being challenged by ARM-based processors from AMD, Broadcom, Marvell (recently acquired Cavium), Mellanox and NXP.

Intel has a clear lead in the general-purpose/server processor market, with the Intel Xeon E5, which has been strengthened by the recent introduction of the Intel Xeon Scalable processors. For less demanding applications Intel also has a strong portfolio of Intel Core i3/i5/i7 and Intel Xeon E3 processors. Key challengers to Intel are the x86-based AMD EPYC and ARM-based processors from Qualcomm and Marvell (Cavium).

Demand for higher-capacity switch chips continues to grow with wide usage of 3.2Tbit/s, 6.4Tbit/s and 12.8Tbit/s switch chips in the latest switch systems and those in development. The dominance of Broadcom in the switch chip market is being challenged by innovative designs from several vendors, including Barefoot and Marvell (Cavium). Other vendors with switch chips include Centec, Innovium, Mellanox and Nephos.

Programmability is key and high-level programming is becoming a requirement. Packet processing performance is increasing with optimized cores and hardware acceleration. Switch chip capacity has been doubling every two years and demand is growing. The fully programmable data plane is a key part of virtualized networks and will be implemented on a mix of processing, switching and FPGA/ASIC technologies.

— Simon Stanley, Analyst at Large, Heavy Reading

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