Agere Brings CMOS to 10-Gig
Typically, high-speed devices are made in silicon germanium (SiGe) or a more exotic material first, then moved to complementary metal-oxide semiconductor (CMOS) processes later. CMOS -- the most commonly used silicon manufacturing process -- allows for cheaper chips that run at lower power, but the resulting signals aren't strong enough to stay coherent at high speeds.
With FlexPHY, Agere becomes only the second company to build a one-chip, serial, 10-Gbit/s Sonet PHY in CMOS, the other being Applied Micro Circuits Corp. (AMCC) (Nasdaq: AMCC) with its SuperPHY, which sampled earlier this year (see AMCC Premieres SuperPHY Family). Broadcom Corp. (Nasdaq: BRCM) comes close, with a 10-Gbit/s PHY product that comes in two chips.
The PHY chip is a multiplexer/demultiplexer combination that sits behind the optics, acting as a liaison between optics and electronics such as the framer. FlexPHY takes 16 streams of roughly 622-Mbit/s apiece and combines them into a single 10-Gbit/s signal. On the receiving end, it does the opposite, breaking an incoming 10-Gbit/s transmission into 622-Mbit/s feeds, which are more easily handled by the internal circuitry of framers, media access controllers (MACs), and other semiconductors.
Those speeds are approximate. FlexPHY handles signals between 9.95 Gbit/s and 10.71 Gbit/s, depending on the particular protocol in use.
Agere had produced a two-chip PHY before, with separate mux and demux chips, in SiGe. The CMOS-based FlexPHY manages even better performance, creating jitter of 30 milli-UI (UI meaning "unit interval," the inverse of frequency) compared with 80 mUI for a typical SiGe part.
That's partly due to the high-end CMOS process used, but it also stems from programmable on-chip elements that can alter the input amplitude and the phase of the clock sample. "It's not just your process, it's how you design your circuitry," says Kourosh Matloubi, FlexPHY product manager. "We know how to design circuits with low jitter."
Agere's next step will be a semiconductor core version of FlexPHY that can be integrated into other chips such as framers and media access controllers.
Whether Agere will rely on SiGe for its first 40-Gbit/s PHY "has not been determined yet," Matloubi says. One key factor will be the evolution of CMOS to line widths of 90 nm (the fashionable term for 0.09 micron), a key step that would increase the performance of "plain" silicon. Given the slow market, 90nm processes might emerge in time for companies like Agere to skip using SiGe for early 40-Gbit/s parts.
— Craig Matsumoto, Senior Editor, Light Reading