Accelerant Goes Binary
The company's AN6620 SerDes chip, announced today, carries all the features of its predecessors, except that it's slower (yes, that's right, slower). The chip runs at 6.25 Gbit/s, as opposed to the 10 Gbit/s Accelerant claims with its PAM4 products (see Accelerant Intros 6.25Gbit/s Transceiver).
Most backplane designs operate on binary signaling, in which every "symbol" is a zero or a one. PAM4 uses two digits, meaning twice as much data can be sent without having to speed up the transmission. The appeal is that OEMs can increase speeds without redesigning backplanes.
PAM4 isn't a complex or experimental technology, but it's still considered a bit weird. Accelerant and Rambus Inc. (Nasdaq: RMBS), with its 10-Gbit/s RaSer X, are among the few companies pushing PAM4 signaling for backplanes. Everybody else uses normal binary signaling, and that includes big names such as Broadcom Corp. (Nasdaq: BRCM), Marvell Technology Group Ltd. (Nasdaq: MRVL), and PMC-Sierra Inc. (Nasdaq: PMCS). And even Rambus' RaSer X can run in binary mode, albeit at slower speeds.
The AN6620 is Accelerant's concession to the dominance of binary signaling, and it will let the company win designs related to older backplanes, but it doesn't signify a change in religion. The company still believes in PAM4, says Bill Hoppin, vice president of marketing.
"For backplanes that are especially nasty and difficult [in terms of crosstalk and interference, not social skills], PAM4 has a lot of value," Hoppin says.
Accelerant even joined the Multilevel Signaling Alliance, a group aiming to develop PAM4 standards, although neither the startup nor the Alliance is divulging much more (see Alliance Targets High-Speed Backplanes).
The AN6620 is set to begin sampling next quarter.
— Craig Matsumoto, Senior Editor, Light Reading
For more about backplane transceivers, see Light Reading's latest taxonomy project -- Who Makes What: Electronic Chips and Backplane Transceivers.