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Accelerant Boosts Backplanes

Startup Accelerant Networks Inc. today plans to announce a transceiver chip that could turn out to be a big deal for vendors developing 10-gig Ethernet equipment (see Accelerant Launches First Product).

The chip promises to boost the capacity of backplanes, the circuit boards that link together line cards in telecom equipment. It also automatically adjusts transmission characteristics in a way that leads to low bit-error rates, according to Accelerant’s CEO, Paul Nahi.

Nahi maintains that backplanes represent the biggest bottleneck in today’s telecom equipment. At high data rates, the copper connections (or "traces") in these backplanes start acting as antennas, creating interference that distorts signals and shortens the distance they can travel.

“The design difficulties are enormous,” says Nahi. “We know a couple of companies that can't ship their boxes because they simply can't get the backplane transceivers to work."

Vendors are beginning to announce transceiver developments that get over this problem by splitting 10-Gbit/s transmissions over four copper connections in backplanes. Each connection actually operates at 3.12 Gbit/s, to allow for the overhead involved in synchronizing signals.

This is defined in XAUI (eXtended Attachment Unit Interface) -- pronounced "Zowie!" -- the emerging 10-gig Ethernet standard from The Institute of Electrical and Electronics Engineers Inc. (IEEE)

Velio Communications Inc. was first to announce developments supporting XAUI last January (see Velio Cleans Up). Last week, Texas Instruments Inc. followed suit (see Texas Instruments Shipping Transceiver). And next week, PMC-Sierra Inc. (Nasdaq: PMCS) looks set to enter the fray with its own high-speed backplane transceiver product.

Accelerant, however, has gone one better than all of these vendors by coming up with a way of supporting 5 Gbit/s per copper connection. The actual channel speed, however, is less than other vendors -- only 2.5 Gbit/s -- because the startup uses a multilevel signaling technique. (Each clock tick sends one symbol, but each symbol contains two bits of data.)

The upshot is Accelerant’s chip is easier to make, even though it delivers higher performance, than competing products, according to Nahi. It's based on 0.25 micron CMOS (complementary metal oxide semiconductor), which isn't a cutting-edge technology. This gives the startup more scope to ramp up speeds further in the future, he claims. Other vendors used “brute force” to get to 3.12 Gbit/s a channel, says Nahi, who contends this gives them less scope for boosting speeds.

Accelerant plans two versions of its chip to start with: one handling a single 5-Gbit/s channel and the other handling five channels, totaling 25 Gbit/s. They’ll be backwards compatible with XAUI, according to Nahi: "Ethernet only specifies a basic SerDes [Serializer/Deserializer -- a parallel to serial converter] function on the chip, so that leaves us plenty of room for creativity."

That creativity is expressed in the form of sophisticated on-chip signal processing capabilities, which perform automatic optimization of the signal level. Nahi explains why this is required: "At one inch [of trace length], you don't want to send a strong signal, because the back reflections will kill you, whereas at 48 inches you've got to have a strong signal in order to go the distance. The transceiver is smart enough to figure all that out."

Velio also claims that its chip can adjust to the signal level using what it calls "pre-emphasis," but it does not do this intelligently, according to Nahi. "With Velio's chip you have to select one of four states, and you do it manually. With our chip, there are 22 million states to chose from, and it's chosen automatically. Furthermore, the chip is continually monitoring the channel characteristics and making adjustments." The bottom line is that bit error rate should be lower.

Velio wasn’t available for comment on these claims. However, it's worth pointing out that Velio's master plan calls for integration of its high-speed SerDes function with a high port-count switching fabric -- taking it into a different marketplace (see Velio Breaks Grooming Barrier.)

In contrast, Accelerant is tightly focussed on backplane communications. Dr. Howard Johnson, an acknowledged industry guru on backplane designs, is one of the founders and sits on the advisory board. The other founders were Nahi and VP for sales Jim Tavacoli, both of whom hail from the Microelectronics division of NEC Corp. (Nasdaq: NIPNY). The startup's CTO, Jim Gorecki, was a founder and former CTO of Level One Communications Inc., a fabless chip maker that was acquired by Intel in 1999.

Accelerant was founded in October 1999 and has $14 million of funding from Mohr Davidow Ventures and Goldman Sachs & Co. (NYSE: GS).

— Pauline Rigby, Senior Editor, Light Reading http://www.lightreading.com

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BlueWater66 12/4/2012 | 8:38:15 PM
re: Accelerant Boosts Backplanes I find it hard to believe an electrical TRV can transmit 2.5~3.125 Gb/s through 48" of trace AND two backplane electrical connectors (one IN and one OUT). I'd guess maximum of 5". I think most of these people are pushing the edge of electrical intraconnects and denying that optical backplanes are about to take over. There seems to be a large engineering customer base that is afraid of optics and willing to keep struggling with older, tired technologies! I also question the BER robustness of multi-level analog signals.
Dr. Freud 12/4/2012 | 8:38:13 PM
re: Accelerant Boosts Backplanes I agree. A great ultra-short haul solution.

Dr. Freud 12/4/2012 | 8:38:12 PM
re: Accelerant Boosts Backplanes I agree. A great ultra-short haul solution.

wlry02 12/4/2012 | 8:38:08 PM
re: Accelerant Boosts Backplanes Who are the companies that are doing the optical backplane.

One of the problem is that optical backplane is not intelligent enough right now.
boson3 12/4/2012 | 8:38:07 PM
re: Accelerant Boosts Backplanes
Be awful funny to a see a product without a backplane, although in Europe you cant access the backplane from the backplane, you have to access the backplane from the frontplane.

Any product doing OC carrier work has an optical backplane.

Hope this helps!



jim_baldwin 12/4/2012 | 8:38:07 PM
re: Accelerant Boosts Backplanes There is a significant body of research that has been done on multi-gigabit electrical transmission across copper lines. I support your skepticism, but encourage you to do some web surfing on pre-emphasis and equalization techniques. In fact I have seen in our lab 2.5 gbit signals travel through 36" AND two backplane connectors.

I suppose I am part of the large engineering customer base that intentionally avoids using optics. My question would be, doesn't component cost factor into transceiver selection? Aren't optical transceivers/couplers/backplanes more expensive than electrical equivalents which have many more years of cost reduction to their benefit?
BlueWater66 12/4/2012 | 8:38:06 PM
re: Accelerant Boosts Backplanes At the simplest level, look at optical fabrics from companies like Tyco and Molex. These contain a large number embedded fibers. There are also number of parallel optical modules to mate with these.

From a cost perspective, I believe something like a 48"+ electrical backplane that could handle a large number of 2.5~3.125 Gb/s is extremely expensive. Core routers, switches and (especially) clustered systems are all going towards optical backplanes.

Also, look at some of the Infiniband distributed optical mesh developments. I know of a number of core carrier class devices sampling/prototyping today with optical backplanes. I think the enterprise segment is still 2-3 years out.
manoflalambda 12/4/2012 | 8:38:06 PM
re: Accelerant Boosts Backplanes jim... I agree. I haven't yet seen an optical solution, including the optical transmitters and receivers, that might be lower cost for the application than the matching electrical solution. Perhaps with low cost LED or vixel (vecsel? [sp] ) based solutions?

As for vendors, several (Litton, Canon (?) ) are working on ways to imbed fibre into layers (along with other layers of electrical - or one solution with little etched trenches for the fibers) and then add some sort of right-angle connector (perhaps a small imbedded mirror at the end of the fiber?). Optical backplanes still look to be 2-3 years out...

Salute,
Manoflalambda
Half-Inch Stud 12/4/2012 | 8:38:03 PM
re: Accelerant Boosts Backplanes ...Perhaps the optical interconnect modules may be lower cost than the electrical differential interconnect cables...when assessed per channel.

Overall, the optical backplane is dramatically lower cost, and more dense, with nanosecond electrical switch functions in place, by the dozen...when assessed per channel.
Sounds redundant, but there is a different point being made here.

Then consider scale-up on the deployed non-blocking switch [Clos 5-stage] arrangement...I'd figure upgrades to the optical cross-connect is more plug&play. I have difficulty grasping the practicality of a Terabit-level electrical Backplane PCB design in : complexity, thickness, signal integrity, power dissipation [>1KWatt per 72 x 72 OC48 switchboard], etc.

That's my story and I'm sticking to it.

H.I. Stud


Vo 12/4/2012 | 8:38:02 PM
re: Accelerant Boosts Backplanes These guys came in, while I was at Lucent.
What they don't tell you in the Lightreading report is that they have found a way to squeeze more bandwidth out of existing backpalnes. If they are successful, why would anybody want to bother going to a new optical back plane.
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