Accelerant Boosts Backplanes
The chip promises to boost the capacity of backplanes, the circuit boards that link together line cards in telecom equipment. It also automatically adjusts transmission characteristics in a way that leads to low bit-error rates, according to Accelerant’s CEO, Paul Nahi.
Nahi maintains that backplanes represent the biggest bottleneck in today’s telecom equipment. At high data rates, the copper connections (or "traces") in these backplanes start acting as antennas, creating interference that distorts signals and shortens the distance they can travel.
“The design difficulties are enormous,” says Nahi. “We know a couple of companies that can't ship their boxes because they simply can't get the backplane transceivers to work."
Vendors are beginning to announce transceiver developments that get over this problem by splitting 10-Gbit/s transmissions over four copper connections in backplanes. Each connection actually operates at 3.12 Gbit/s, to allow for the overhead involved in synchronizing signals.
This is defined in XAUI (eXtended Attachment Unit Interface) -- pronounced "Zowie!" -- the emerging 10-gig Ethernet standard from The Institute of Electrical and Electronics Engineers Inc. (IEEE)
Velio Communications Inc. was first to announce developments supporting XAUI last January (see Velio Cleans Up). Last week, Texas Instruments Inc. followed suit (see Texas Instruments Shipping Transceiver). And next week, PMC-Sierra Inc. (Nasdaq: PMCS) looks set to enter the fray with its own high-speed backplane transceiver product.
Accelerant, however, has gone one better than all of these vendors by coming up with a way of supporting 5 Gbit/s per copper connection. The actual channel speed, however, is less than other vendors -- only 2.5 Gbit/s -- because the startup uses a multilevel signaling technique. (Each clock tick sends one symbol, but each symbol contains two bits of data.)
The upshot is Accelerant’s chip is easier to make, even though it delivers higher performance, than competing products, according to Nahi. It's based on 0.25 micron CMOS (complementary metal oxide semiconductor), which isn't a cutting-edge technology. This gives the startup more scope to ramp up speeds further in the future, he claims. Other vendors used “brute force” to get to 3.12 Gbit/s a channel, says Nahi, who contends this gives them less scope for boosting speeds.
Accelerant plans two versions of its chip to start with: one handling a single 5-Gbit/s channel and the other handling five channels, totaling 25 Gbit/s. They’ll be backwards compatible with XAUI, according to Nahi: "Ethernet only specifies a basic SerDes [Serializer/Deserializer -- a parallel to serial converter] function on the chip, so that leaves us plenty of room for creativity."
That creativity is expressed in the form of sophisticated on-chip signal processing capabilities, which perform automatic optimization of the signal level. Nahi explains why this is required: "At one inch [of trace length], you don't want to send a strong signal, because the back reflections will kill you, whereas at 48 inches you've got to have a strong signal in order to go the distance. The transceiver is smart enough to figure all that out."
Velio also claims that its chip can adjust to the signal level using what it calls "pre-emphasis," but it does not do this intelligently, according to Nahi. "With Velio's chip you have to select one of four states, and you do it manually. With our chip, there are 22 million states to chose from, and it's chosen automatically. Furthermore, the chip is continually monitoring the channel characteristics and making adjustments." The bottom line is that bit error rate should be lower.
Velio wasn’t available for comment on these claims. However, it's worth pointing out that Velio's master plan calls for integration of its high-speed SerDes function with a high port-count switching fabric -- taking it into a different marketplace (see Velio Breaks Grooming Barrier.)
In contrast, Accelerant is tightly focussed on backplane communications. Dr. Howard Johnson, an acknowledged industry guru on backplane designs, is one of the founders and sits on the advisory board. The other founders were Nahi and VP for sales Jim Tavacoli, both of whom hail from the Microelectronics division of NEC Corp. (Nasdaq: NIPNY). The startup's CTO, Jim Gorecki, was a founder and former CTO of Level One Communications Inc., a fabless chip maker that was acquired by Intel in 1999.
Accelerant was founded in October 1999 and has $14 million of funding from Mohr Davidow Ventures and Goldman Sachs & Co. (NYSE: GS).
— Pauline Rigby, Senior Editor, Light Reading http://www.lightreading.com