The GigaChip Interface (GCI) is a scalable, high-performance, serial protocol for chip-to-chip communications that is differentiated in efficiency and reliability, resulting in system level benefits of reduced power, cost and complexity. Current implementations built with compatible CEI-11G or XFI SerDes electrical transport standards deliver up to 144Gbps of full duplex data throughput using 16 serdes lanes when running at a 10G rate. A key differentiator for the GCI protocol is high transport efficiency, even for small payloads. Alternative serial interfaces are typically less than 50 percent efficient when transferring 8B and 16B data, which means that they deliver less than half the performance at a given bandwidth. The combination of 90 percent transport efficiency, from small to large payloads, combined with power efficient short reach physical interconnect makes GCI ideal for co-processor, memory, or multi-chip communication. The interface also includes CRC error detection and automatic error recovery provisions to meet the high reliability requirements of enterprise, service provider, and mission critical communications and compute applications. GCI is an open, royalty-free, interface specification designed for use with the MoSys Bandwidth Engine family of ICs and is suitable for any chip-to-chip interconnect.

“As a leading ASIC provider to the industry, we see a major trend towards serial chip-to-chip interconnect, which is necessary to enable systems at 100G and beyond,” said Akira Denda, General Manager, 2nd Industrial Network Business Division of Renesas Electronics Corp. “We believe the GigaChip Interface provides the reliability, performance, efficiency, and openness needed, and we are pleased to expand our strong IP portfolio for our networking ASIC customers.”

Renesas Electronics Corp.