As network performance and feature requirements continue to scale, architectural improvements are required. Networking equipment has transitioned to highly parallel, multi-threaded processing System-on-Chip complexes which require an insatiable amount of memory bandwidth. The Bandwidth Engine 2 family has three purpose-built variants, Burst, Access and Macro, to meet these growing needs and is intended for high-reliability, carrier-grade applications.
Using sixteen 15 Gigabits per second (Gbps) SerDes lanes, the Bandwidth Engine 2 interface operates at 480 Gbps, providing the host with up to 384 Gbps CRC protected, effective data throughput. This represents an unprecedented 80% overall efficiency, well beyond the capability of standard memory subsystems and alternative serial interface solutions, while using less than half of the board area, interface pins, and power resulting in substantial system-level cost savings.
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