Ciena Corp. (Nasdaq: CIEN) is announcing its next 100Gbit/s optical processor on Thursday, readying itself for the 400Gbit/s generation.
The WaveLogic 3 chip promises to extend 100Gbit/s reach to 2,500 km without regeneration, through technologies including soft forward error correction (FEC).
The chip also uses a digital signal processor (DSP) on the transmit side. This opens the possibility to mess with 100Gbit/s wavelengths, squashing them into a space smaller than the usual 50GHz spacing, so that more wavelengths can fit on a fiber.
WaveLogic 3 also takes advantage of increased processing smarts. For example, it can be programmed to make tradeoffs -- improving latency by lightening up on FEC, and therefore giving up some reach.
Ciena expects to have customers running live traffic on WaveLogic 3 this year.
Why this matters
This means the 400Gbit/s generation is almost underway, although Ciena expects it to happen in a limited fashion and doesn't expect customer deployments until 2013.
The real importance is on the 100Gbit/s side, where longer reach and lower power are going to be key topics this year. Cisco already declared the ability to run 100Gbit/s wavelengths for 3,000 km without regeneration, as EANTC verified in its recent test of Cisco CloudVerse, and we'll probably hear plenty more about 100Gbit/s improvements during OFC/NFOEC next week.
A couple of other things to note: Ciena will continue using an in-house chip for its next 100Gbit/s generation, showing the power of vertical integration.
And with the transmit DSP, and the ability to squeeze more wavelengths together, it's setting up applications for flexible-grid reconfigurable optical add/drop multiplexers (ROADM)s in the 100Gbit/s generation. It's suspected that a flexible grid will be useful as the industry approaches 1Tbit/s.
Ciena put together this video to show the thing in action:
For more
Keep up with our coverage on the Light ReadingOFC/NFOEC site.
Good point - I agree. That said, I would think metro regional is up to 1000km but the implication from Ciena is that the reach is somewhat less than that achieved by a 200Gbps single channel.
Doesn't make sense -- Ciena's 200G uses QAM16 in a 50GHz channel (hence the shorter reach), surely their 400G uses 2 bonded 200G QAM16 50GHz channels so the reach will be the same?
(I doubt that it uses QAM256 in 1 channel, OSNR and reach would be awful...)
IIRC ALU's paper at ECOC used 45Gbaud QAM32 to do 400G in a single channel with 75GHz optical bandwidth, this would presumably have shorter reach than QAM16 but would need faster sampling (90Gs/s?) wider bandwidth (30GHz?) ADCs and DACs.
Ciena will need two WaveLogic 3 chipsets for 400Gbps. The WaveLogic 3, on a 32nm process, is a two-device chipset (the transmit and receive coherent DSP ASICs). And to your point, Chandan, Ciena says 400G will have a metro regional reach while 200Gbps will achieve 750-1000km. Impressive but as you say, not 100Gbps reaches yet.
Other vendors (e.g. NEL) already have 100G single-carrier transceivers with soft FEC, so this isn't new -- what is new is integrating the TX MUX/DAC function, but it's not a surprise given Ciena's paper about their DAC published last year.
I think I left this part unclear: You need two Wavelogic 3 chips to make 400G; each one does 200G. So you'd need two lasers as well.
Sterling Perrin at Heavy Reading points out that this is Ciena's debut of a single-carrier 100G (versus dual carrier in one 50GHz spacing). So Ciena will catch up to Alcatel-Lucent on that front.
The real challenge for R&D is to match reach of 400G and 100G with that of 40G and 10G so that operators can plan smooth upgrades without increasing touch points. Similarly 1T per lambda later to match reach of 100G and 400G
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