SAN JOSE, Calif. -- Cypress Semiconductor Corp. (NYSE:CY) today expanded its networking-optimized, 18-Mbit SRAM portfolio to include a variety of new options to better serve next-generation communications requirements. It is now sampling both the No Bus Latency™ (NoBLTM) and standard synchronous architecture SRAMs, targeting a broad range of networking and telecom segments, including wireless infrastructure (WIN), wide area networks (WAN), and storage array networks (SAN).

The pipelined and flowthrough versions of NoBL and standard synchronous devices are now available in 1024K x 18 and 512K x 36 configurations at 3.3-V and 2.5-V. The 2.5-V offering addresses the trend toward lower operating voltages. These parts consume less power than earlier-generation 5-V devices and are ideal for interfacing with the 2.5-V ASIC devices used in the networking systems being developed today. The flowthrough versions of these devices support bus speeds up to 115 MHz; the pipelined versions support bus speeds up to 200 MHz. These 0.15-micron devices offer high density, low operating power and fast data transfer.

"The expansion of our 18-Mbit family provides Cypress a leadership position in synchronous, networking-optimized memories, strengthening significantly what has become a $200M a year business for us," said Tony Alvarez, senior vice president of Cypress's Memory Products Division. "Our expanded portfolio is a direct response to the needs of our strategic communications accounts, to whom we already provide a broad range of solutions in logic, timing technology, specialty memories, and physical-layer devices."

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