Field-programmable gate arrays (FPGAs) have become mainstays in systems design, but Xilinx Inc. (Nasdaq: XLNX) sees a chance to nibble even further into the part of the market that used to belong to ASICs.

The company's Virtex-6 and Spartan-6 families, introduced Monday, represent the newest iteration of Xilinx's FPGAs, with the usual advances, including more circuitry available and lower power consumption for functions implemented on-chip. (See Xilinx Adds Two.)

But Xilinx is also using this chip generation as a chance to push a marketing message -- that FPGAs have grown beyond their traditional prototyping role and could play an even bigger role in systems design.

FPGAs are like sketchpads. They're programmable to resemble all sorts of different chips. For that reason, they've been used for rough drafts: An engineer spins an FPGA to check a design, then, once it's perfected, moves the design into a specialized chip -- either an application-specific integrated circuit (ASIC), for specialty uses, or an application-specific standard product (ASSP) intended for a mass market.

That's how it's been done for generations. (Meaning chip generations, not people generations. Xilinx is only 25 years old.) Because FPGAs are bigger, slower, and more power-hungry than specialized chips, it usually paid off to move to an ASIC or ASSP later.

But in recent years, the costs of ASICs have gone out of reach for many applications. That's got some systems companies looking into alternatives, Xilinx claims.

"They can't justify the huge investment in the design team," let alone the costs of designing, building, and revising these chips, Xilinx CEO Moshe Gavrielov says.

Everyone likes to root for Moore's Law, which in loose terms predicts that each generation of chips will carry more stuff. But Moore's Law relies on chip circuitry shrinking every few years, and the smaller features have made cutting-edge chips more expensive to develop. That price can reach $100 million if you're using state-of-the-art 32nm process technology, according to Gavrielov.

Neither can systems companies hope for chip startups to develop the products they need, since that tier of companies has "basically gone away" due to lack of funding, says Gavrielov.

What systems makers really want, he says, is a partially pre-built chip, one that covers the 80 percent of a job that's mundane but leaves room for the systems vendor to add customization. It's similar to what the systems vendors say they're doing for the carriers: providing equipment that's mostly standardized but leaves room for the customization of services.

FPGAs have long been moving towards that goal, and Xilinx is making it a big part of the Virtex-6 and Spartan-6 launch. (Think of the Spartan-6 as a low-end version of the Virtex-6.) The chips come with the usual programmable logic array and can accommodate pre-built units called "cores," but Xilinx also wants to provide market-specific blocks and interfaces, moving the FPGAs even one step closer to being finished products.

One example would be Forward Error Correction (FEC) -- upgradable to enhanced forward error correction (EFEC) -- for optical transport network (OTN) interfaces. Another would be on-chip signal processing for wireless communications, helping create a better signal so that base stations can use lower-power amplifiers.

The Virtex-6 and Spartan-6 are set to ship in the second quarter of this year, with market-specific versions coming out in the first quarter of 2010.

Xilinx is being particularly aggressive, but it's not alone in trying to move FPGAs into the roles some ASICs used to play. Tpack A/S builds its TPX3103, a prefab carrier Ethernet switch sold to OEMs, out of FPGAs from Altera Corp. (Nasdaq: ALTR). And a new version, the TPX4004, packing Altera's Stratix IV chips, is due out very soon, Tpack CTO Lars Pedersen said recently.

Speaking at a carrier Ethernet seminar put on last week by The Linley Group , Pedersen noted that power consumption on the newest FPGAs is lower by "30 to 40 percent compared to previous generations." (Chip geeks: He's talking about 40nm line widths.)

But Pedersen conceded that fixed-function chips can do even better. "If you can get an ASSP to do exactly what you need to do, inherently that would be more cost-effective," he said. To that end, he noted that some customers have turned Tpack designs into "hard-copy" chips -- that is, replacing the FPGAs with corresponding ASICs. Customers did that on their own, though; it's not an option Tpack sells.

Customer systems using the TPX4004 could be ready by the end of the year.

— Craig Matsumoto, West Coast Editor, Light Reading