A few semiconductor vendors now say they can encapsulate an entire line card into a programmable chip, an achievement they're hoping will spawn new generations of networking equipment as 100Gbit/s speeds begin to take hold.

Three examples were presented in papers Thursday at the Linley Tech Processor Conference. The annual technology-focused event, put on by The Linley Group, has become, among other things, a focal point for discussing the network processors that drive switches and routers.

EZchip Technologies Ltd. (Nasdaq: EZCH), for the first time, disclosed details of its upcoming NPS network processor -- an entirely new category of network processor, according to Linley Group analyst Bob Wheeler -- during Thursday's session. In addition, Netronome presented its NFP-6000 family, which was announced in June, while Tilera Corp. presented its TILE-Gx processors.

EZchip and Netronome both sell network processors -- chips specifically designed for networking equipment -- and both say they're expanding their scope to cover Layers 2 through 7, thanks to their new chip designs. That means they can target switching, routing, security, deep packet inspection -- pretty much all the intelligence in a network element.

Tilera's chips are multicore processors applicable to a variety of purposes, including video transcoding. Tilera is a competitor in the line-card market, too, but it's not as dependent on that market as the other two.

Meanwhile, router vendors are stretching to the upper layers more frequently themselves, adding more intelligence for functions such as security, load balancing or content delivery networks. Juniper Networks Inc. (NYSE: JNPR) offered some recent examples with a handful of router announcements. (See Juniper Primes Its Edge Router Lineup and Juniper Claims Edge Enhancements.)



Processor clash
You could say EZchip and Netronome are getting to this destination from opposite directions. EZchip sells network processors that handle switching and routing -- Layers 2 and 3 -- and is expanding up to Layer 7 with the NPS.

EZchip built its business on the NP line of network processors. Originally aimed at core routers, back when core-router startups actually existed, the chips ended up finding their way into Cisco and Juniper router/switch designs for the network edge.

"Two and a half years ago, we saw where carrier networks were heading, requiring more and more bandwidth but also requiring more intelligent packet processing," said Amir Eyal, EZchip's vice president of business development, during a quick chat with Light Reading.

Netronome was more a Layer 4-through-7 company, making boards that went into security appliances and similar types of networking gear. But it has its own Layer 2 and 3 capabilities with the NFP line of network processors, which it licensed from Intel Corp. (Nasdaq: INTC) in 2007. (See Netronome Reigniting Intel's IXP.)

Netronome is combining those aspects of its business with the NFP-6000 line, which will use 216 processing cores, 96 of them being a new type that handles packet classification. The chips are due to sample in mid-2013. (See Netronome Boasts of a 200G Processor.)

EZchip's NPS isn't going to sample until late in 2013. The company announced the general structure of the chip in September, but meatier engineering details were kept under wraps until Thursday's Linley conference session. The chip is a revamp of EZchip's current NP-4 processor and represents the company's long-term future.

The road to NPS
EZchip wanted to revamp the NP to handle services -- security and the like -- and also wanted the chip to be programmable in the C language, which is well known. NPs have to be programmed in EZchip's own programming lnguage.

"C programming was the target for us," said Guy Koren, vice president technology and CTO. But he also noted that EZchip wanted to avoid having data run back and forth between chips, something that can happen when processing traffic at multiple layers.

The answer to the second problem was to combine everything into one chip. As a result, the NPS uses a type of core that combines the NP's packet-processing cores with the attributes of general-purpose central processing units (CPUs). In a sense, EZchip absorbed the multicore CPU that would often sit next to an NP, creating a new, hybrid type of chip.

It's a subtle difference from Netronome's chip, which uses two different types of processor cores.

The NPS isn't going to even sample until late 2013, in 200Gbit/s and 400Gbit/s throughput versions. EZchip is talking about it now partly because officials expect most NP customers to move to NPS chips eventually. The NP will continue progressing, with the NP-5 expected to sample soon and an NP-6 design on the roadmap, for customers that don't want to port their software to C for the NPS.

Business-wise, this will take EZchip beyond its switch/router roots and into a wider venue that looks more like, well, like Netronome's business.

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The fine print
This wasn't lost on Netronome, and it made for a few points of contention when EZchip, Netronome and Tilera got to contrast their approaches during a Q&A at the Linley Group conference.

One debate had to do with what it takes to process packets at Layers 2 through 7. Netronome considers Layers 2 and 3 -- switching and routing -- to be known cases that require less programmability. The more flexible elements of its chip are devoted to the harder Layer 4-through-7 cases, Proch said.

"We pulled the well understood stuff out. We put that in the Layer 2 and 3 cores," Proch said.

EZchip disagreed that Layers 2 and 3 are so well defined. Koren repeated his point that the packets sometimes need to get processed multiple times, depending on what the chip finds out about them.

"We have found that Layer 2 and Layer 3 are not so well defined as people think," Koren said. "It is a very dynamic type of operation."

Netronome also called out EZchip for supporting Linux on each of its processor cores. "To pack it tight, you gotta keep it light," Proch said, channeling his inner Johnnie Cochran.

Koren admitted that Linux comes with some overhead but called it minimal, a one-time sacrifice. Once a flow is established and is being processed, the performance is the same as on "bare metal," he said -- that is, without an operating system.

It turns out Tilera feels the same way about running Linux on its cores. "We agree with that, and we've been doing that for two years," said Bob Doud, Tilera's director of processor strategy.

— Craig Matsumoto, Managing Editor, Light Reading